llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

; %D4 should be zero-initialized for gfx1250, which only supports 4 groups of tensor descriptor
declare void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
declare void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
declare void @llvm.amdgcn.asyncmark()
declare void @llvm.amdgcn.wait.asyncmark(i16)
declare void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %src, ptr addrspace(3) %dst, i32 %offset, i32 %cpol)

define amdgpu_ps void @tensor_load_to_lds_d4(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
; GFX1250-LABEL: tensor_load_to_lds_d4:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 0)
  ret void
}

define amdgpu_ps void @tensor_load_to_lds_d4_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
; GFX1250-SDAG-LABEL: tensor_load_to_lds_d4_vector:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s12, v12
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s13, v13
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s14, v14
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s15, v15
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s16, v16
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s17, v17
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s18, v18
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s19, v19
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: tensor_load_to_lds_d4_vector:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s12, v12
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s13, v13
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s14, v14
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s15, v15
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s16, v16
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s17, v17
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s18, v18
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s19, v19
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]
; GFX1250-GISEL-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 0)
  ret void
}

define amdgpu_ps void @tensor_load_to_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_load_to_lds_d2:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27)
  ret void
}

define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
; GFX1250-SDAG-LABEL: tensor_load_to_lds_d2_vector:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: tensor_load_to_lds_d2_vector:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-GISEL-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_d4(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
; GFX1250-LABEL: tensor_store_from_lds_d4:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 22)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_d4_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
; GFX1250-SDAG-LABEL: tensor_store_from_lds_d4_vector:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s12, v12
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s13, v13
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s14, v14
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s15, v15
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s16, v16
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s17, v17
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s18, v18
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s19, v19
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: tensor_store_from_lds_d4_vector:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s12, v12
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s13, v13
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s14, v14
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s15, v15
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s16, v16
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s17, v17
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s18, v18
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s19, v19
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-GISEL-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 22)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_store_from_lds_d2:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_store_from_lds s[0:3], s[4:11]
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
; GFX1250-SDAG-LABEL: tensor_store_from_lds_d2_vector:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDAG-NEXT:    tensor_store_from_lds s[8:11], s[0:7]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: tensor_store_from_lds_d2_vector:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s9, v1
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s10, v2
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s11, v3
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v4
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v5
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v6
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v7
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s4, v8
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s5, v9
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s6, v10
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s7, v11
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT:    tensor_store_from_lds s[8:11], s[0:7]
; GFX1250-GISEL-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  ret void
}

;=======================================================================
; It is fine to pass 5 arguments as tensor descriptor, but the fifth one
; will be ignored silently by the CodeGen for gfx1250, which only
; supports D# up to 4 groups.
;========================================================================

define amdgpu_ps void @tensor_load_to_lds_d5(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg %D4) {
; GFX1250-LABEL: tensor_load_to_lds_d5:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 0)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_d5(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg %D4) {
; GFX1250-LABEL: tensor_store_from_lds_d5:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 22)
  ret void
}

;=======================================================================
; Tensor load/store DMAs are asynchronous and tracked via TENSOR_CNT.
; Verify that they participate in the asyncmark / wait_asyncmark
; mechanism.
;========================================================================

define amdgpu_ps void @tensor_load_to_lds_with_asyncmark(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_load_to_lds_with_asyncmark:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[4:11]
; GFX1250-NEXT:    ; asyncmark
; GFX1250-NEXT:    ; wait_asyncmark(0)
; GFX1250-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()
  call void @llvm.amdgcn.wait.asyncmark(i16 0)
  ret void
}

define amdgpu_ps void @tensor_store_from_lds_with_asyncmark(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
; GFX1250-LABEL: tensor_store_from_lds_with_asyncmark:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_store_from_lds s[0:3], s[4:11]
; GFX1250-NEXT:    ; asyncmark
; GFX1250-NEXT:    ; wait_asyncmark(0)
; GFX1250-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()
  call void @llvm.amdgcn.wait.asyncmark(i16 0)
  ret void
}

; Two outstanding tensor loads tracked by separate asyncmarks. The first
; wait_asyncmark(1) drains down to one outstanding TENSOR_CNT entry, the
; second wait_asyncmark(0) drains the remaining one.
define amdgpu_ps void @tensor_load_to_lds_two_asyncmarks(<4 x i32> inreg %D0a, <8 x i32> inreg %D1a, <4 x i32> inreg %D0b, <8 x i32> inreg %D1b, ptr addrspace(3) %lds) {
; GFX1250-LABEL: tensor_load_to_lds_two_asyncmarks:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[4:11]
; GFX1250-NEXT:    ; asyncmark
; GFX1250-NEXT:    s_wait_tensorcnt 0xa
; GFX1250-NEXT:    tensor_load_to_lds s[12:15], s[16:23]
; GFX1250-NEXT:    ; asyncmark
; GFX1250-NEXT:    ; wait_asyncmark(1)
; GFX1250-NEXT:    s_wait_tensorcnt 0x1
; GFX1250-NEXT:    ds_load_b32 v1, v0
; GFX1250-NEXT:    ; wait_asyncmark(0)
; GFX1250-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-NEXT:    ds_load_b32 v2, v0 offset:4
; GFX1250-NEXT:    s_wait_dscnt 0x0
; GFX1250-NEXT:    v_add_nc_u32_e32 v1, v1, v2
; GFX1250-NEXT:    ds_store_b32 v0, v1
; GFX1250-NEXT:    s_endpgm
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0a, <8 x i32> %D1a, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()

  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0b, <8 x i32> %D1b, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()

  call void @llvm.amdgcn.wait.asyncmark(i16 1)
  %lds_v0 = load i32, ptr addrspace(3) %lds

  call void @llvm.amdgcn.wait.asyncmark(i16 0)
  %lds_gep1 = getelementptr i32, ptr addrspace(3) %lds, i32 1
  %lds_v1 = load i32, ptr addrspace(3) %lds_gep1

  %sum = add i32 %lds_v0, %lds_v1
  store i32 %sum, ptr addrspace(3) %lds

  ret void
}

;=======================================================================
; Mix ASYNC_CNT and TENSOR_CNT tracked operations under a single
; asyncmark, and verify that a wait.asyncmark drains both counters.
;========================================================================

define void @tensor_and_async_lds_with_asyncmark(<4 x i32> inreg %D0, <8 x i32> inreg %D1, ptr addrspace(1) %src, ptr addrspace(3) %dst) {
; GFX1250-LABEL: tensor_and_async_lds_with_asyncmark:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_load_async_to_lds_b32 v2, v[0:1], off
; GFX1250-NEXT:    tensor_load_to_lds s[0:3], s[16:23]
; GFX1250-NEXT:    ; asyncmark
; GFX1250-NEXT:    ; wait_asyncmark(0)
; GFX1250-NEXT:    s_wait_asynccnt 0x0
; GFX1250-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
  call void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %src, ptr addrspace(3) %dst, i32 0, i32 0)
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()
  call void @llvm.amdgcn.wait.asyncmark(i16 0)
  ret void
}

;=======================================================================
; Two diamond if/else regions, each picking either a tensor DMA or an
; async-LDS DMA, each followed by its own asyncmark.
;========================================================================

define void @tensor_or_async_lds_diamonds(i32 inreg %cond1, i32 inreg %cond2, <4 x i32> inreg %D0, <8 x i32> inreg %D1, ptr addrspace(1) %src, ptr addrspace(3) %dst) {
; GFX1250-SDAG-LABEL: tensor_or_async_lds_diamonds:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_mov_b32 s11, s25
; GFX1250-SDAG-NEXT:    s_mov_b32 s10, s24
; GFX1250-SDAG-NEXT:    s_mov_b32 s9, s23
; GFX1250-SDAG-NEXT:    s_mov_b32 s8, s22
; GFX1250-SDAG-NEXT:    s_mov_b32 s7, s21
; GFX1250-SDAG-NEXT:    s_mov_b32 s6, s20
; GFX1250-SDAG-NEXT:    s_mov_b32 s5, s19
; GFX1250-SDAG-NEXT:    s_mov_b32 s4, s18
; GFX1250-SDAG-NEXT:    s_mov_b32 s15, s17
; GFX1250-SDAG-NEXT:    s_mov_b32 s14, s16
; GFX1250-SDAG-NEXT:    s_mov_b32 s13, s3
; GFX1250-SDAG-NEXT:    s_mov_b32 s12, s2
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s0, 0
; GFX1250-SDAG-NEXT:    s_cbranch_scc1 .LBB14_3
; GFX1250-SDAG-NEXT:  ; %bb.1: ; %t1
; GFX1250-SDAG-NEXT:    tensor_load_to_lds s[12:15], s[4:11]
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s1, 0
; GFX1250-SDAG-NEXT:    ; asyncmark
; GFX1250-SDAG-NEXT:    s_cbranch_scc1 .LBB14_4
; GFX1250-SDAG-NEXT:  .LBB14_2: ; %t2
; GFX1250-SDAG-NEXT:    s_wait_tensorcnt 0xa
; GFX1250-SDAG-NEXT:    tensor_load_to_lds s[12:15], s[4:11]
; GFX1250-SDAG-NEXT:    ; asyncmark
; GFX1250-SDAG-NEXT:    ; wait_asyncmark(1)
; GFX1250-SDAG-NEXT:    s_wait_asynccnt 0x0
; GFX1250-SDAG-NEXT:    s_wait_tensorcnt 0x1
; GFX1250-SDAG-NEXT:    s_set_pc_i64 s[30:31]
; GFX1250-SDAG-NEXT:  .LBB14_3: ; %g1
; GFX1250-SDAG-NEXT:    global_load_async_to_lds_b32 v2, v[0:1], off
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s1, 0
; GFX1250-SDAG-NEXT:    ; asyncmark
; GFX1250-SDAG-NEXT:    s_cbranch_scc0 .LBB14_2
; GFX1250-SDAG-NEXT:  .LBB14_4: ; %g2
; GFX1250-SDAG-NEXT:    global_load_async_to_lds_b32 v2, v[0:1], off
; GFX1250-SDAG-NEXT:    ; asyncmark
; GFX1250-SDAG-NEXT:    ; wait_asyncmark(1)
; GFX1250-SDAG-NEXT:    s_wait_asynccnt 0x1
; GFX1250-SDAG-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-SDAG-NEXT:    s_set_pc_i64 s[30:31]
;
; GFX1250-GISEL-LABEL: tensor_or_async_lds_diamonds:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_mov_b32 s12, s2
; GFX1250-GISEL-NEXT:    s_mov_b32 s13, s3
; GFX1250-GISEL-NEXT:    s_mov_b32 s14, s16
; GFX1250-GISEL-NEXT:    s_mov_b32 s15, s17
; GFX1250-GISEL-NEXT:    s_mov_b32 s4, s18
; GFX1250-GISEL-NEXT:    s_mov_b32 s5, s19
; GFX1250-GISEL-NEXT:    s_mov_b32 s6, s20
; GFX1250-GISEL-NEXT:    s_mov_b32 s7, s21
; GFX1250-GISEL-NEXT:    s_mov_b32 s8, s22
; GFX1250-GISEL-NEXT:    s_mov_b32 s9, s23
; GFX1250-GISEL-NEXT:    s_mov_b32 s10, s24
; GFX1250-GISEL-NEXT:    s_mov_b32 s11, s25
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s0, 0
; GFX1250-GISEL-NEXT:    s_cbranch_scc1 .LBB14_3
; GFX1250-GISEL-NEXT:  ; %bb.1: ; %t1
; GFX1250-GISEL-NEXT:    tensor_load_to_lds s[12:15], s[4:11]
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s1, 0
; GFX1250-GISEL-NEXT:    ; asyncmark
; GFX1250-GISEL-NEXT:    s_cbranch_scc1 .LBB14_4
; GFX1250-GISEL-NEXT:  .LBB14_2: ; %t2
; GFX1250-GISEL-NEXT:    s_wait_tensorcnt 0xa
; GFX1250-GISEL-NEXT:    tensor_load_to_lds s[12:15], s[4:11]
; GFX1250-GISEL-NEXT:    ; asyncmark
; GFX1250-GISEL-NEXT:    ; wait_asyncmark(1)
; GFX1250-GISEL-NEXT:    s_wait_asynccnt 0x0
; GFX1250-GISEL-NEXT:    s_wait_tensorcnt 0x1
; GFX1250-GISEL-NEXT:    s_set_pc_i64 s[30:31]
; GFX1250-GISEL-NEXT:  .LBB14_3: ; %g1
; GFX1250-GISEL-NEXT:    global_load_async_to_lds_b32 v2, v[0:1], off
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s1, 0
; GFX1250-GISEL-NEXT:    ; asyncmark
; GFX1250-GISEL-NEXT:    s_cbranch_scc0 .LBB14_2
; GFX1250-GISEL-NEXT:  .LBB14_4: ; %g2
; GFX1250-GISEL-NEXT:    global_load_async_to_lds_b32 v2, v[0:1], off
; GFX1250-GISEL-NEXT:    ; asyncmark
; GFX1250-GISEL-NEXT:    ; wait_asyncmark(1)
; GFX1250-GISEL-NEXT:    s_wait_asynccnt 0x1
; GFX1250-GISEL-NEXT:    s_wait_tensorcnt 0x0
; GFX1250-GISEL-NEXT:    s_set_pc_i64 s[30:31]
entry:
  %c1 = icmp ne i32 %cond1, 0
  br i1 %c1, label %t1, label %g1

t1:
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()
  br label %merge1

g1:
  call void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %src, ptr addrspace(3) %dst, i32 0, i32 0)
  call void @llvm.amdgcn.asyncmark()
  br label %merge1

merge1:
  %c2 = icmp ne i32 %cond2, 0
  br i1 %c2, label %t2, label %g2

t2:
  call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
  call void @llvm.amdgcn.asyncmark()
  br label %merge2

g2:
  call void @llvm.amdgcn.global.load.async.to.lds.b32(ptr addrspace(1) %src, ptr addrspace(3) %dst, i32 0, i32 0)
  call void @llvm.amdgcn.asyncmark()
  br label %merge2

merge2:
  call void @llvm.amdgcn.wait.asyncmark(i16 1)
  ret void
}