llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load-exported.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=amdgcn -mcpu=verde | FileCheck %s --check-prefixes=PREGFX10
;RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefixes=PREGFX10
;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefixes=GFX10
;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11

define amdgpu_ps void @buffer_load_x1_offen_merged_and(ptr addrspace(8) inreg %rsrc, i32 %a) {
; PREGFX10-LABEL: buffer_load_x1_offen_merged_and:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
; PREGFX10-NEXT:    buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
; PREGFX10-NEXT:    s_waitcnt vmcnt(1)
; PREGFX10-NEXT:    exp mrt0, v1, v2, v3, v4 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v5, v6, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x1_offen_merged_and:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    s_clause 0x1
; GFX10-NEXT:    buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX10-NEXT:    buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    exp mrt0, v1, v2, v3, v4 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v5, v6, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x1_offen_merged_and:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    buffer_load_b128 v[1:4], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT:    buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    exp mrt0, v1, v2, v3, v4 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v5, v6, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %a1 = add i32 %a, 4
  %a2 = add i32 %a, 8
  %a3 = add i32 %a, 12
  %a4 = add i32 %a, 16
  %a5 = add i32 %a, 28
  %a6 = add i32 %a, 32
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a1, i32 0, i32 0)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a2, i32 0, i32 0)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a3, i32 0, i32 0)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a4, i32 0, i32 0)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x1_offen_merged_or(ptr addrspace(8) inreg %rsrc, i32 %inp) {
; PREGFX10-LABEL: buffer_load_x1_offen_merged_or:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    v_lshlrev_b32_e32 v4, 6, v0
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], v4, s[0:3], 0 offen offset:4
; PREGFX10-NEXT:    buffer_load_dwordx2 v[4:5], v4, s[0:3], 0 offen offset:28
; PREGFX10-NEXT:    s_waitcnt vmcnt(1)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x1_offen_merged_or:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 6, v0
; GFX10-NEXT:    s_clause 0x1
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 offen offset:4
; GFX10-NEXT:    buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 offen offset:28
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x1_offen_merged_or:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 6, v0
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:4
; GFX11-NEXT:    buffer_load_b64 v[4:5], v4, s[0:3], 0 offen offset:28
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v4, v5, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %a = shl i32 %inp, 6
  %a1 = or i32 %a, 4
  %a2 = or i32 %a, 8
  %a3 = or i32 %a, 12
  %a4 = or i32 %a, 16
  %a5 = or i32 %a, 28
  %a6 = or i32 %a, 32
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a1, i32 0, i32 0)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a2, i32 0, i32 0)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a3, i32 0, i32 0)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a4, i32 0, i32 0)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 0)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 0)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(ptr addrspace(8) inreg %rsrc, i32 %a) {
; PREGFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
; PREGFX10-NEXT:    buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
; PREGFX10-NEXT:    buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
; PREGFX10-NEXT:    s_waitcnt vmcnt(1)
; PREGFX10-NEXT:    exp mrt0, v1, v2, v3, v4 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v5, v6, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    s_clause 0x2
; GFX10-NEXT:    buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
; GFX10-NEXT:    buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
; GFX10-NEXT:    buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    exp mrt0, v1, v2, v3, v4 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v5, v6, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x1_offen_merged_glc_slc:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x2
; GFX11-NEXT:    buffer_load_b64 v[1:2], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT:    buffer_load_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc
; GFX11-NEXT:    buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    exp mrt0, v1, v2, v3, v4 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v5, v6, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %a1 = add i32 %a, 4
  %a2 = add i32 %a, 8
  %a3 = add i32 %a, 12
  %a4 = add i32 %a, 16
  %a5 = add i32 %a, 28
  %a6 = add i32 %a, 32
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a1, i32 0, i32 0)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a2, i32 0, i32 0)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a3, i32 0, i32 1)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a4, i32 0, i32 1)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a5, i32 0, i32 3)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 %a6, i32 0, i32 3)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x2_offen_merged_and(ptr addrspace(8) inreg %rsrc, i32 %a) {
; PREGFX10-LABEL: buffer_load_x2_offen_merged_and:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x2_offen_merged_and:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x2_offen_merged_and:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_endpgm
main_body:
  %a1 = add i32 %a, 4
  %a2 = add i32 %a, 12
  %vr1 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %a1, i32 0, i32 0)
  %vr2 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %a2, i32 0, i32 0)
  %r1 = extractelement <2 x float> %vr1, i32 0
  %r2 = extractelement <2 x float> %vr1, i32 1
  %r3 = extractelement <2 x float> %vr2, i32 0
  %r4 = extractelement <2 x float> %vr2, i32 1
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x2_offen_merged_or(ptr addrspace(8) inreg %rsrc, i32 %inp) {
; PREGFX10-LABEL: buffer_load_x2_offen_merged_or:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x2_offen_merged_or:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x2_offen_merged_or:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
; GFX11-NEXT:    buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_endpgm
main_body:
  %a = shl i32 %inp, 4
  %a1 = add i32 %a, 4
  %a2 = add i32 %a, 12
  %vr1 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %a1, i32 0, i32 0)
  %vr2 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %a2, i32 0, i32 0)
  %r1 = extractelement <2 x float> %vr1, i32 0
  %r2 = extractelement <2 x float> %vr1, i32 1
  %r3 = extractelement <2 x float> %vr2, i32 0
  %r4 = extractelement <2 x float> %vr2, i32 1
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x1_offset_merged(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-LABEL: buffer_load_x1_offset_merged:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; PREGFX10-NEXT:    buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
; PREGFX10-NEXT:    s_waitcnt vmcnt(1)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x1_offset_merged:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    s_clause 0x1
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; GFX10-NEXT:    buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x1_offset_merged:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v4, v5, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 8, i32 0, i32 0)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 12, i32 0, i32 0)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 16, i32 0, i32 0)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @buffer_load_x2_offset_merged(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-LABEL: buffer_load_x2_offset_merged:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: buffer_load_x2_offset_merged:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: buffer_load_x2_offset_merged:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_endpgm
main_body:
  %vr1 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0)
  %vr2 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 12, i32 0, i32 0)
  %r1 = extractelement <2 x float> %vr1, i32 0
  %r2 = extractelement <2 x float> %vr1, i32 1
  %r3 = extractelement <2 x float> %vr2, i32 0
  %r4 = extractelement <2 x float> %vr2, i32 1
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_merged(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-LABEL: raw_ptr_buffer_load_x1_offset_merged:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; PREGFX10-NEXT:    buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
; PREGFX10-NEXT:    s_waitcnt vmcnt(1)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: raw_ptr_buffer_load_x1_offset_merged:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    s_clause 0x1
; GFX10-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
; GFX10-NEXT:    buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
; GFX10-NEXT:    s_waitcnt vmcnt(1)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: raw_ptr_buffer_load_x1_offset_merged:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
; GFX11-NEXT:    buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
; GFX11-NEXT:    s_waitcnt vmcnt(1)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v4, v5, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 8, i32 0, i32 0)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 12, i32 0, i32 0)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 16, i32 0, i32 0)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 0)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 0)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}

define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_swizzled_not_merged(ptr addrspace(8) inreg %rsrc) {
; PREGFX10-LABEL: raw_ptr_buffer_load_x1_offset_swizzled_not_merged:
; PREGFX10:       ; %bb.0: ; %main_body
; PREGFX10-NEXT:    buffer_load_dword v0, off, s[0:3], 0 offset:4
; PREGFX10-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:8
; PREGFX10-NEXT:    buffer_load_dword v2, off, s[0:3], 0 offset:12
; PREGFX10-NEXT:    buffer_load_dword v3, off, s[0:3], 0 offset:16
; PREGFX10-NEXT:    buffer_load_dword v4, off, s[0:3], 0 offset:28
; PREGFX10-NEXT:    buffer_load_dword v5, off, s[0:3], 0 offset:32
; PREGFX10-NEXT:    s_waitcnt vmcnt(2)
; PREGFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; PREGFX10-NEXT:    s_waitcnt vmcnt(0)
; PREGFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; PREGFX10-NEXT:    s_endpgm
;
; GFX10-LABEL: raw_ptr_buffer_load_x1_offset_swizzled_not_merged:
; GFX10:       ; %bb.0: ; %main_body
; GFX10-NEXT:    s_clause 0x5
; GFX10-NEXT:    buffer_load_dword v0, off, s[0:3], 0 offset:4
; GFX10-NEXT:    buffer_load_dword v1, off, s[0:3], 0 offset:8
; GFX10-NEXT:    buffer_load_dword v2, off, s[0:3], 0 offset:12
; GFX10-NEXT:    buffer_load_dword v3, off, s[0:3], 0 offset:16
; GFX10-NEXT:    buffer_load_dword v4, off, s[0:3], 0 offset:28
; GFX10-NEXT:    buffer_load_dword v5, off, s[0:3], 0 offset:32
; GFX10-NEXT:    s_waitcnt vmcnt(2)
; GFX10-NEXT:    exp mrt0, v0, v1, v2, v3 done vm
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    exp mrt0, v4, v5, v0, v0 done vm
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: raw_ptr_buffer_load_x1_offset_swizzled_not_merged:
; GFX11:       ; %bb.0: ; %main_body
; GFX11-NEXT:    s_clause 0x5
; GFX11-NEXT:    buffer_load_b32 v0, off, s[0:3], 0 offset:4
; GFX11-NEXT:    buffer_load_b32 v1, off, s[0:3], 0 offset:8
; GFX11-NEXT:    buffer_load_b32 v2, off, s[0:3], 0 offset:12
; GFX11-NEXT:    buffer_load_b32 v3, off, s[0:3], 0 offset:16
; GFX11-NEXT:    buffer_load_b32 v4, off, s[0:3], 0 offset:28
; GFX11-NEXT:    buffer_load_b32 v5, off, s[0:3], 0 offset:32
; GFX11-NEXT:    s_waitcnt vmcnt(2)
; GFX11-NEXT:    exp mrt0, v0, v1, v2, v3 done
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    exp mrt0, v4, v5, v0, v0 done
; GFX11-NEXT:    s_endpgm
main_body:
  %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 8)
  %r2 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 8, i32 0, i32 8)
  %r3 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 12, i32 0, i32 8)
  %r4 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 16, i32 0, i32 8)
  %r5 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 28, i32 0, i32 8)
  %r6 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 32, i32 0, i32 8)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float poison, float poison, i1 true, i1 true)
  ret void
}


declare float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32) #0
declare <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8), i32, i32, i32) #0
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
attributes #0 = { nounwind readonly }