[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.
These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.
Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D104822
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 8869299..7cdec14 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1609,4 +1609,41 @@
def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUv", "csil">;
}
}
+
+ let Name = "vget_v",
+ ManualCodegen = [{
+ {
+ ID = Intrinsic::experimental_vector_extract;
+ ScalableVectorType *VecTy = cast<ScalableVectorType>(ResultType);
+ Ops[1] = Builder.CreateMul(Ops[1],
+ ConstantInt::get(Ops[1]->getType(),
+ VecTy->getMinNumElements()));
+ IntrinsicTypes = {ResultType, Ops[0]->getType()};
+ return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
+ }
+ }] in {
+ foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
+ def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilfd">;
+ def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil">;
+ }
+ }
+
+ let Name = "vset_v", Log2LMUL = [0, 1, 2],
+ ManualCodegen = [{
+ {
+ ID = Intrinsic::experimental_vector_insert;
+ IntrinsicTypes = {ResultType, Ops[2]->getType()};
+ ScalableVectorType *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
+ Ops[1] = Builder.CreateMul(Ops[1],
+ ConstantInt::get(Ops[1]->getType(),
+ VecTy->getMinNumElements()));
+ std::swap(Ops[1], Ops[2]);
+ return Builder.CreateCall(CGM.getIntrinsic(ID, IntrinsicTypes), Ops, "");
+ }
+ }] in {
+ foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
+ def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilfd">;
+ def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
+ }
+ }
}
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 561c83e..17eeebb 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3488,6 +3488,132 @@
case RISCV::BI__builtin_rvv_vsetvlimax:
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
CheckRISCVLMUL(TheCall, 1);
+ case RISCV::BI__builtin_rvv_vget_v_i8m2_i8m1:
+ case RISCV::BI__builtin_rvv_vget_v_i16m2_i16m1:
+ case RISCV::BI__builtin_rvv_vget_v_i32m2_i32m1:
+ case RISCV::BI__builtin_rvv_vget_v_i64m2_i64m1:
+ case RISCV::BI__builtin_rvv_vget_v_f32m2_f32m1:
+ case RISCV::BI__builtin_rvv_vget_v_f64m2_f64m1:
+ case RISCV::BI__builtin_rvv_vget_v_u8m2_u8m1:
+ case RISCV::BI__builtin_rvv_vget_v_u16m2_u16m1:
+ case RISCV::BI__builtin_rvv_vget_v_u32m2_u32m1:
+ case RISCV::BI__builtin_rvv_vget_v_u64m2_u64m1:
+ case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m2:
+ case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m2:
+ case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m2:
+ case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m2:
+ case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m2:
+ case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m2:
+ case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m2:
+ case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m2:
+ case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m2:
+ case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m2:
+ case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m4:
+ case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m4:
+ case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m4:
+ case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m4:
+ case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m4:
+ case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m4:
+ case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m4:
+ case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m4:
+ case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m4:
+ case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m4:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+ case RISCV::BI__builtin_rvv_vget_v_i8m4_i8m1:
+ case RISCV::BI__builtin_rvv_vget_v_i16m4_i16m1:
+ case RISCV::BI__builtin_rvv_vget_v_i32m4_i32m1:
+ case RISCV::BI__builtin_rvv_vget_v_i64m4_i64m1:
+ case RISCV::BI__builtin_rvv_vget_v_f32m4_f32m1:
+ case RISCV::BI__builtin_rvv_vget_v_f64m4_f64m1:
+ case RISCV::BI__builtin_rvv_vget_v_u8m4_u8m1:
+ case RISCV::BI__builtin_rvv_vget_v_u16m4_u16m1:
+ case RISCV::BI__builtin_rvv_vget_v_u32m4_u32m1:
+ case RISCV::BI__builtin_rvv_vget_v_u64m4_u64m1:
+ case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m2:
+ case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m2:
+ case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m2:
+ case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m2:
+ case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m2:
+ case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m2:
+ case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m2:
+ case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m2:
+ case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m2:
+ case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m2:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
+ case RISCV::BI__builtin_rvv_vget_v_i8m8_i8m1:
+ case RISCV::BI__builtin_rvv_vget_v_i16m8_i16m1:
+ case RISCV::BI__builtin_rvv_vget_v_i32m8_i32m1:
+ case RISCV::BI__builtin_rvv_vget_v_i64m8_i64m1:
+ case RISCV::BI__builtin_rvv_vget_v_f32m8_f32m1:
+ case RISCV::BI__builtin_rvv_vget_v_f64m8_f64m1:
+ case RISCV::BI__builtin_rvv_vget_v_u8m8_u8m1:
+ case RISCV::BI__builtin_rvv_vget_v_u16m8_u16m1:
+ case RISCV::BI__builtin_rvv_vget_v_u32m8_u32m1:
+ case RISCV::BI__builtin_rvv_vget_v_u64m8_u64m1:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
+ case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m2:
+ case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m2:
+ case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m2:
+ case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m2:
+ case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m2:
+ case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m2:
+ case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m2:
+ case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m2:
+ case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m2:
+ case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m2:
+ case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m4:
+ case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m4:
+ case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m4:
+ case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m4:
+ case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m4:
+ case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m4:
+ case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m4:
+ case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m4:
+ case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m4:
+ case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m4:
+ case RISCV::BI__builtin_rvv_vset_v_i8m4_i8m8:
+ case RISCV::BI__builtin_rvv_vset_v_i16m4_i16m8:
+ case RISCV::BI__builtin_rvv_vset_v_i32m4_i32m8:
+ case RISCV::BI__builtin_rvv_vset_v_i64m4_i64m8:
+ case RISCV::BI__builtin_rvv_vset_v_f32m4_f32m8:
+ case RISCV::BI__builtin_rvv_vset_v_f64m4_f64m8:
+ case RISCV::BI__builtin_rvv_vset_v_u8m4_u8m8:
+ case RISCV::BI__builtin_rvv_vset_v_u16m4_u16m8:
+ case RISCV::BI__builtin_rvv_vset_v_u32m4_u32m8:
+ case RISCV::BI__builtin_rvv_vset_v_u64m4_u64m8:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+ case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m4:
+ case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m4:
+ case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m4:
+ case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m4:
+ case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m4:
+ case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m4:
+ case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m4:
+ case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m4:
+ case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m4:
+ case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m4:
+ case RISCV::BI__builtin_rvv_vset_v_i8m2_i8m8:
+ case RISCV::BI__builtin_rvv_vset_v_i16m2_i16m8:
+ case RISCV::BI__builtin_rvv_vset_v_i32m2_i32m8:
+ case RISCV::BI__builtin_rvv_vset_v_i64m2_i64m8:
+ case RISCV::BI__builtin_rvv_vset_v_f32m2_f32m8:
+ case RISCV::BI__builtin_rvv_vset_v_f64m2_f64m8:
+ case RISCV::BI__builtin_rvv_vset_v_u8m2_u8m8:
+ case RISCV::BI__builtin_rvv_vset_v_u16m2_u16m8:
+ case RISCV::BI__builtin_rvv_vset_v_u32m2_u32m8:
+ case RISCV::BI__builtin_rvv_vset_v_u64m2_u64m8:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
+ case RISCV::BI__builtin_rvv_vset_v_i8m1_i8m8:
+ case RISCV::BI__builtin_rvv_vset_v_i16m1_i16m8:
+ case RISCV::BI__builtin_rvv_vset_v_i32m1_i32m8:
+ case RISCV::BI__builtin_rvv_vset_v_i64m1_i64m8:
+ case RISCV::BI__builtin_rvv_vset_v_f32m1_f32m8:
+ case RISCV::BI__builtin_rvv_vset_v_f64m1_f64m8:
+ case RISCV::BI__builtin_rvv_vset_v_u8m1_u8m8:
+ case RISCV::BI__builtin_rvv_vset_v_u16m1_u16m8:
+ case RISCV::BI__builtin_rvv_vset_v_u32m1_u32m8:
+ case RISCV::BI__builtin_rvv_vset_v_u64m1_u64m8:
+ return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7);
}
return false;
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
new file mode 100644
index 0000000..ac287ff
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
@@ -0,0 +1,546 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m2_i8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vget_v_i8m2_i8m1(vint8m2_t src) {
+ return vget_v_i8m2_i8m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vget_v_i8m4_i8m1(vint8m4_t src) {
+ return vget_v_i8m4_i8m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m4_i8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vget_v_i8m4_i8m2(vint8m4_t src) {
+ return vget_v_i8m4_i8m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vget_v_i8m8_i8m1(vint8m8_t src) {
+ return vget_v_i8m8_i8m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vget_v_i8m8_i8m2(vint8m8_t src) {
+ return vget_v_i8m8_i8m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i8m8_i8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vget_v_i8m8_i8m4(vint8m8_t src) {
+ return vget_v_i8m8_i8m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m2_i16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vget_v_i16m2_i16m1(vint16m2_t src) {
+ return vget_v_i16m2_i16m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vget_v_i16m4_i16m1(vint16m4_t src) {
+ return vget_v_i16m4_i16m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m4_i16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vget_v_i16m4_i16m2(vint16m4_t src) {
+ return vget_v_i16m4_i16m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vget_v_i16m8_i16m1(vint16m8_t src) {
+ return vget_v_i16m8_i16m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vget_v_i16m8_i16m2(vint16m8_t src) {
+ return vget_v_i16m8_i16m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i16m8_i16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vget_v_i16m8_i16m4(vint16m8_t src) {
+ return vget_v_i16m8_i16m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m2_i32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vget_v_i32m2_i32m1(vint32m2_t src) {
+ return vget_v_i32m2_i32m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vget_v_i32m4_i32m1(vint32m4_t src) {
+ return vget_v_i32m4_i32m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m4_i32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vget_v_i32m4_i32m2(vint32m4_t src) {
+ return vget_v_i32m4_i32m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vget_v_i32m8_i32m1(vint32m8_t src) {
+ return vget_v_i32m8_i32m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vget_v_i32m8_i32m2(vint32m8_t src) {
+ return vget_v_i32m8_i32m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i32m8_i32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vget_v_i32m8_i32m4(vint32m8_t src) {
+ return vget_v_i32m8_i32m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m2_i64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vget_v_i64m2_i64m1(vint64m2_t src) {
+ return vget_v_i64m2_i64m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vget_v_i64m4_i64m1(vint64m4_t src) {
+ return vget_v_i64m4_i64m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m4_i64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vget_v_i64m4_i64m2(vint64m4_t src) {
+ return vget_v_i64m4_i64m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vget_v_i64m8_i64m1(vint64m8_t src) {
+ return vget_v_i64m8_i64m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vget_v_i64m8_i64m2(vint64m8_t src) {
+ return vget_v_i64m8_i64m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_i64m8_i64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vget_v_i64m8_i64m4(vint64m8_t src) {
+ return vget_v_i64m8_i64m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m2_u8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv16i8(<vscale x 16 x i8> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vget_v_u8m2_u8m1(vuint8m2_t src) {
+ return vget_v_u8m2_u8m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vget_v_u8m4_u8m1(vuint8m4_t src) {
+ return vget_v_u8m4_u8m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m4_u8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vget_v_u8m4_u8m2(vuint8m4_t src) {
+ return vget_v_u8m4_u8m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vector.extract.nxv8i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vget_v_u8m8_u8m1(vuint8m8_t src) {
+ return vget_v_u8m8_u8m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.extract.nxv16i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 48)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vget_v_u8m8_u8m2(vuint8m8_t src) {
+ return vget_v_u8m8_u8m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u8m8_u8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.extract.nxv32i8.nxv64i8(<vscale x 64 x i8> [[SRC:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vget_v_u8m8_u8m4(vuint8m8_t src) {
+ return vget_v_u8m8_u8m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m2_u16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv8i16(<vscale x 8 x i16> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vget_v_u16m2_u16m1(vuint16m2_t src) {
+ return vget_v_u16m2_u16m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vget_v_u16m4_u16m1(vuint16m4_t src) {
+ return vget_v_u16m4_u16m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m4_u16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vget_v_u16m4_u16m2(vuint16m4_t src) {
+ return vget_v_u16m4_u16m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.experimental.vector.extract.nxv4i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vget_v_u16m8_u16m1(vuint16m8_t src) {
+ return vget_v_u16m8_u16m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.extract.nxv8i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vget_v_u16m8_u16m2(vuint16m8_t src) {
+ return vget_v_u16m8_u16m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u16m8_u16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.extract.nxv16i16.nxv32i16(<vscale x 32 x i16> [[SRC:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vget_v_u16m8_u16m4(vuint16m8_t src) {
+ return vget_v_u16m8_u16m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m2_u32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv4i32(<vscale x 4 x i32> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vget_v_u32m2_u32m1(vuint32m2_t src) {
+ return vget_v_u32m2_u32m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vget_v_u32m4_u32m1(vuint32m4_t src) {
+ return vget_v_u32m4_u32m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m4_u32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vget_v_u32m4_u32m2(vuint32m4_t src) {
+ return vget_v_u32m4_u32m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vget_v_u32m8_u32m1(vuint32m8_t src) {
+ return vget_v_u32m8_u32m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vget_v_u32m8_u32m2(vuint32m8_t src) {
+ return vget_v_u32m8_u32m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u32m8_u32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vget_v_u32m8_u32m4(vuint32m8_t src) {
+ return vget_v_u32m8_u32m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m2_u64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv2i64(<vscale x 2 x i64> [[SRC:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vget_v_u64m2_u64m1(vuint64m2_t src) {
+ return vget_v_u64m2_u64m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vget_v_u64m4_u64m1(vuint64m4_t src) {
+ return vget_v_u64m4_u64m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m4_u64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vget_v_u64m4_u64m2(vuint64m4_t src) {
+ return vget_v_u64m4_u64m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.experimental.vector.extract.nxv1i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vget_v_u64m8_u64m1(vuint64m8_t src) {
+ return vget_v_u64m8_u64m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.extract.nxv2i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vget_v_u64m8_u64m2(vuint64m8_t src) {
+ return vget_v_u64m8_u64m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_u64m8_u64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.extract.nxv4i64.nxv8i64(<vscale x 8 x i64> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vget_v_u64m8_u64m4(vuint64m8_t src) {
+ return vget_v_u64m8_u64m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m2_f32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv4f32(<vscale x 4 x float> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vget_v_f32m2_f32m1(vfloat32m2_t src) {
+ return vget_v_f32m2_f32m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vget_v_f32m4_f32m1(vfloat32m4_t src) {
+ return vget_v_f32m4_f32m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m4_f32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv8f32(<vscale x 8 x float> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vget_v_f32m4_f32m2(vfloat32m4_t src) {
+ return vget_v_f32m4_f32m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.experimental.vector.extract.nxv2f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
+//
+vfloat32m1_t test_vget_v_f32m8_f32m1(vfloat32m8_t src) {
+ return vget_v_f32m8_f32m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.extract.nxv4f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vget_v_f32m8_f32m2(vfloat32m8_t src) {
+ return vget_v_f32m8_f32m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f32m8_f32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.extract.nxv8f32.nxv16f32(<vscale x 16 x float> [[SRC:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
+//
+vfloat32m4_t test_vget_v_f32m8_f32m4(vfloat32m8_t src) {
+ return vget_v_f32m8_f32m4(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m2_f64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv2f64(<vscale x 2 x double> [[SRC:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vget_v_f64m2_f64m1(vfloat64m2_t src) {
+ return vget_v_f64m2_f64m1(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vget_v_f64m4_f64m1(vfloat64m4_t src) {
+ return vget_v_f64m4_f64m1(src, 2);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m4_f64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv4f64(<vscale x 4 x double> [[SRC:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
+//
+vfloat64m2_t test_vget_v_f64m4_f64m2(vfloat64m4_t src) {
+ return vget_v_f64m4_f64m2(src, 1);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
+//
+vfloat64m1_t test_vget_v_f64m8_f64m1(vfloat64m8_t src) {
+ return vget_v_f64m8_f64m1(src, 6);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.extract.nxv2f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
+//
+vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src) {
+ return vget_v_f64m8_f64m2(src, 3);
+}
+
+// CHECK-RV64-LABEL: @test_vget_v_f64m8_f64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.extract.nxv4f64.nxv8f64(<vscale x 8 x double> [[SRC:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
+//
+vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src) {
+ return vget_v_f64m8_f64m4(src, 1);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
new file mode 100644
index 0000000..95da801
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
@@ -0,0 +1,546 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+ return vset_v_i8m1_i8m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+ return vset_v_i8m1_i8m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+ return vset_v_i8m2_i8m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m1_i8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+ return vset_v_i8m1_i8m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m2_i8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+ return vset_v_i8m2_i8m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i8m4_i8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+ return vset_v_i8m4_i8m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+ return vset_v_i16m1_i16m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+ return vset_v_i16m1_i16m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+ return vset_v_i16m2_i16m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m1_i16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
+ return vset_v_i16m1_i16m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m2_i16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) {
+ return vset_v_i16m2_i16m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i16m4_i16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, vint16m4_t val) {
+ return vset_v_i16m4_i16m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, vint32m1_t val) {
+ return vset_v_i32m1_i32m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, vint32m1_t val) {
+ return vset_v_i32m1_i32m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, vint32m2_t val) {
+ return vset_v_i32m2_i32m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m1_i32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, vint32m1_t val) {
+ return vset_v_i32m1_i32m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m2_i32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, vint32m2_t val) {
+ return vset_v_i32m2_i32m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i32m4_i32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, vint32m4_t val) {
+ return vset_v_i32m4_i32m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, vint64m1_t val) {
+ return vset_v_i64m1_i64m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vset_v_i64m1_i64m4(vint64m4_t dest, vint64m1_t val) {
+ return vset_v_i64m1_i64m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vint64m4_t test_vset_v_i64m2_i64m4(vint64m4_t dest, vint64m2_t val) {
+ return vset_v_i64m2_i64m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m1_i64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vset_v_i64m1_i64m8(vint64m8_t dest, vint64m1_t val) {
+ return vset_v_i64m1_i64m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m2_i64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vset_v_i64m2_i64m8(vint64m8_t dest, vint64m2_t val) {
+ return vset_v_i64m2_i64m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_i64m4_i64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vint64m8_t test_vset_v_i64m4_i64m8(vint64m8_t dest, vint64m4_t val) {
+ return vset_v_i64m4_i64m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.nxv8i8(<vscale x 16 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
+//
+vuint8m2_t test_vset_v_u8m1_u8m2(vuint8m2_t dest, vuint8m1_t val) {
+ return vset_v_u8m1_u8m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv8i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 24)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vset_v_u8m1_u8m4(vuint8m4_t dest, vuint8m1_t val) {
+ return vset_v_u8m1_u8m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.experimental.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
+//
+vuint8m4_t test_vset_v_u8m2_u8m4(vuint8m4_t dest, vuint8m2_t val) {
+ return vset_v_u8m2_u8m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m1_u8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv8i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 8 x i8> [[VAL:%.*]], i64 56)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vset_v_u8m1_u8m8(vuint8m8_t dest, vuint8m1_t val) {
+ return vset_v_u8m1_u8m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m2_u8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv16i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 16 x i8> [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vset_v_u8m2_u8m8(vuint8m8_t dest, vuint8m2_t val) {
+ return vset_v_u8m2_u8m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u8m4_u8m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.experimental.vector.insert.nxv64i8.nxv32i8(<vscale x 64 x i8> [[DEST:%.*]], <vscale x 32 x i8> [[VAL:%.*]], i64 32)
+// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
+//
+vuint8m8_t test_vset_v_u8m4_u8m8(vuint8m8_t dest, vuint8m4_t val) {
+ return vset_v_u8m4_u8m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.insert.nxv8i16.nxv4i16(<vscale x 8 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
+//
+vuint16m2_t test_vset_v_u16m1_u16m2(vuint16m2_t dest, vuint16m1_t val) {
+ return vset_v_u16m1_u16m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv4i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 12)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vset_v_u16m1_u16m4(vuint16m4_t dest, vuint16m1_t val) {
+ return vset_v_u16m1_u16m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.experimental.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
+//
+vuint16m4_t test_vset_v_u16m2_u16m4(vuint16m4_t dest, vuint16m2_t val) {
+ return vset_v_u16m2_u16m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m1_u16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv4i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 4 x i16> [[VAL:%.*]], i64 28)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vset_v_u16m1_u16m8(vuint16m8_t dest, vuint16m1_t val) {
+ return vset_v_u16m1_u16m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m2_u16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv8i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 8 x i16> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vset_v_u16m2_u16m8(vuint16m8_t dest, vuint16m2_t val) {
+ return vset_v_u16m2_u16m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u16m4_u16m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.experimental.vector.insert.nxv32i16.nxv16i16(<vscale x 32 x i16> [[DEST:%.*]], <vscale x 16 x i16> [[VAL:%.*]], i64 16)
+// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
+//
+vuint16m8_t test_vset_v_u16m4_u16m8(vuint16m8_t dest, vuint16m4_t val) {
+ return vset_v_u16m4_u16m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.nxv2i32(<vscale x 4 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
+//
+vuint32m2_t test_vset_v_u32m1_u32m2(vuint32m2_t dest, vuint32m1_t val) {
+ return vset_v_u32m1_u32m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv2i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vset_v_u32m1_u32m4(vuint32m4_t dest, vuint32m1_t val) {
+ return vset_v_u32m1_u32m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.experimental.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
+//
+vuint32m4_t test_vset_v_u32m2_u32m4(vuint32m4_t dest, vuint32m2_t val) {
+ return vset_v_u32m2_u32m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m1_u32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv2i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 2 x i32> [[VAL:%.*]], i64 14)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vset_v_u32m1_u32m8(vuint32m8_t dest, vuint32m1_t val) {
+ return vset_v_u32m1_u32m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m2_u32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 4 x i32> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vset_v_u32m2_u32m8(vuint32m8_t dest, vuint32m2_t val) {
+ return vset_v_u32m2_u32m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u32m4_u32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv16i32.nxv8i32(<vscale x 16 x i32> [[DEST:%.*]], <vscale x 8 x i32> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
+//
+vuint32m8_t test_vset_v_u32m4_u32m8(vuint32m8_t dest, vuint32m4_t val) {
+ return vset_v_u32m4_u32m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.insert.nxv2i64.nxv1i64(<vscale x 2 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
+//
+vuint64m2_t test_vset_v_u64m1_u64m2(vuint64m2_t dest, vuint64m1_t val) {
+ return vset_v_u64m1_u64m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv1i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vset_v_u64m1_u64m4(vuint64m4_t dest, vuint64m1_t val) {
+ return vset_v_u64m1_u64m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.experimental.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
+//
+vuint64m4_t test_vset_v_u64m2_u64m4(vuint64m4_t dest, vuint64m2_t val) {
+ return vset_v_u64m2_u64m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m1_u64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv1i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 1 x i64> [[VAL:%.*]], i64 7)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vset_v_u64m1_u64m8(vuint64m8_t dest, vuint64m1_t val) {
+ return vset_v_u64m1_u64m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m2_u64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv2i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 2 x i64> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vset_v_u64m2_u64m8(vuint64m8_t dest, vuint64m2_t val) {
+ return vset_v_u64m2_u64m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_u64m4_u64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.experimental.vector.insert.nxv8i64.nxv4i64(<vscale x 8 x i64> [[DEST:%.*]], <vscale x 4 x i64> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
+//
+vuint64m8_t test_vset_v_u64m4_u64m8(vuint64m8_t dest, vuint64m4_t val) {
+ return vset_v_u64m4_u64m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.experimental.vector.insert.nxv4f32.nxv2f32(<vscale x 4 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vset_v_f32m1_f32m2(vfloat32m2_t dest, vfloat32m1_t val) {
+ return vset_v_f32m1_f32m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv2f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 6)
+// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
+//
+vfloat32m4_t test_vset_v_f32m1_f32m4(vfloat32m4_t dest, vfloat32m1_t val) {
+ return vset_v_f32m1_f32m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.experimental.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
+//
+vfloat32m4_t test_vset_v_f32m2_f32m4(vfloat32m4_t dest, vfloat32m2_t val) {
+ return vset_v_f32m2_f32m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m1_f32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv2f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 2 x float> [[VAL:%.*]], i64 14)
+// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
+//
+vfloat32m8_t test_vset_v_f32m1_f32m8(vfloat32m8_t dest, vfloat32m1_t val) {
+ return vset_v_f32m1_f32m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m2_f32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv4f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 4 x float> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
+//
+vfloat32m8_t test_vset_v_f32m2_f32m8(vfloat32m8_t dest, vfloat32m2_t val) {
+ return vset_v_f32m2_f32m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f32m4_f32m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.experimental.vector.insert.nxv16f32.nxv8f32(<vscale x 16 x float> [[DEST:%.*]], <vscale x 8 x float> [[VAL:%.*]], i64 8)
+// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
+//
+vfloat32m8_t test_vset_v_f32m4_f32m8(vfloat32m8_t dest, vfloat32m4_t val) {
+ return vset_v_f32m4_f32m8(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.experimental.vector.insert.nxv2f64.nxv1f64(<vscale x 2 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
+//
+vfloat64m2_t test_vset_v_f64m1_f64m2(vfloat64m2_t dest, vfloat64m1_t val) {
+ return vset_v_f64m1_f64m2(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv1f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
+//
+vfloat64m4_t test_vset_v_f64m1_f64m4(vfloat64m4_t dest, vfloat64m1_t val) {
+ return vset_v_f64m1_f64m4(dest, 3, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.experimental.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
+//
+vfloat64m4_t test_vset_v_f64m2_f64m4(vfloat64m4_t dest, vfloat64m2_t val) {
+ return vset_v_f64m2_f64m4(dest, 1, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m1_f64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv1f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 1 x double> [[VAL:%.*]], i64 7)
+// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
+//
+vfloat64m8_t test_vset_v_f64m1_f64m8(vfloat64m8_t dest, vfloat64m1_t val) {
+ return vset_v_f64m1_f64m8(dest, 7, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m2_f64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv2f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 2 x double> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
+//
+vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, vfloat64m2_t val) {
+ return vset_v_f64m2_f64m8(dest, 2, val);
+}
+
+// CHECK-RV64-LABEL: @test_vset_v_f64m4_f64m8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.experimental.vector.insert.nxv8f64.nxv4f64(<vscale x 8 x double> [[DEST:%.*]], <vscale x 4 x double> [[VAL:%.*]], i64 4)
+// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
+//
+vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, vfloat64m4_t val) {
+ return vset_v_f64m4_f64m8(dest, 1, val);
+}
