| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --replace-value-regex "!llvm.loop ![0-9]+" --version 6 |
| ; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S | FileCheck --check-prefixes=COMMON,CHECK,NOSTRIDED %s |
| ; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -force-vector-interleave=2 -S | FileCheck --check-prefixes=COMMON,CHECK-UF2,NOSTRIDED-UF2 %s |
| ; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -lv-strided-pointer-ivs=true -laa-speculate-unit-stride=false -S | FileCheck --check-prefixes=COMMON,STRIDED-COMMON,CHECK,STRIDED %s |
| ; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -lv-strided-pointer-ivs=true -laa-speculate-unit-stride=false -force-vector-interleave=2 -S | FileCheck --check-prefixes=COMMON,STRIDED-COMMON,CHECK-UF2,STRIDED-UF2 %s |
| |
| |
| define void @single_constant_stride_int_scaled(ptr %p) { |
| ; CHECK-LABEL: define void @single_constant_stride_int_scaled( |
| ; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[INDEX]], 5 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP5]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP6]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]]) |
| ; CHECK-NEXT: [[TMP16:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP16]], ptr align 4 [[TMP6]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]]) |
| ; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP12]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP12]] |
| ; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @single_constant_stride_int_scaled( |
| ; CHECK-UF2-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 [[TMP1]], i64 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[TMP6]] |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = shl i64 [[INDEX]], 5 |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP16]] |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = mul i64 [[TMP3]], 32 |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP17]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP8]]) |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP19]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP8]]) |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER1]], splat (i32 1) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP13]], ptr align 4 [[TMP17]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP8]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP14]], ptr align 4 [[TMP19]], i64 32, <vscale x 4 x i1> splat (i1 true), i32 [[TMP8]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], 8 |
| ; CHECK-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; CHECK-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; CHECK-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; CHECK-UF2-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; CHECK-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| |
| %offset = mul nsw nuw i64 %i, 8 |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %q0 |
| |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @single_constant_stride_int_iv(ptr %p) { |
| ; CHECK-LABEL: define void @single_constant_stride_int_iv( |
| ; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP8]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP9]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-NEXT: [[TMP13:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP13]], ptr align 4 [[TMP9]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP7]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP11]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]] |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @single_constant_stride_int_iv( |
| ; CHECK-UF2-SAME: ptr [[P:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = shl i64 [[N_VEC]], 6 |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP3]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = shl i64 [[INDEX]], 8 |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP16]] |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = mul i64 [[TMP3]], 256 |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP18]] |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP17]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER1:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP14]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER1]], splat (i32 1) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP11]], ptr align 4 [[TMP17]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP12]], ptr align 4 [[TMP14]], i64 256, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[OFFSET:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; CHECK-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; CHECK-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; CHECK-UF2-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; CHECK-UF2-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], 64 |
| ; CHECK-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %offset = phi i64 [0, %entry], [%offset.next, %loop] |
| |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %q0 |
| |
| %offset.next = add nsw nuw i64 %offset, 64 |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| |
| define void @single_constant_stride_ptr_iv(ptr %p) { |
| ; CHECK-LABEL: define void @single_constant_stride_ptr_iv( |
| ; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr nuw i8, ptr [[P]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP19:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP6]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]]) |
| ; CHECK-NEXT: [[TMP20:%.*]] = add <vscale x 4 x i32> [[TMP19]], splat (i32 1) |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP20]], ptr align 4 [[TMP6]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP11]]) |
| ; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP11]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP9]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP9]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @single_constant_stride_ptr_iv( |
| ; CHECK-UF2-SAME: ptr [[P:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 [[TMP1]], i64 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[TMP6]] |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = shl i64 [[N_VEC]], 3 |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP7]] |
| ; CHECK-UF2-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP3]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = shl i64 [[INDEX]], 3 |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = add i64 [[TMP3]], 0 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 8 |
| ; CHECK-UF2-NEXT: [[TMP22:%.*]] = add i64 [[TMP9]], [[TMP11]] |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]] |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP22]] |
| ; CHECK-UF2-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i32>, ptr [[TMP12]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC]]) |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC1:%.*]] = load <vscale x 8 x i32>, ptr [[TMP14]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC2:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC1]]) |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = add <vscale x 4 x i32> [[TMP13]], splat (i32 1) |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = add <vscale x 4 x i32> [[TMP15]], splat (i32 1) |
| ; CHECK-UF2-NEXT: [[TMP23:%.*]] = shl nuw i64 [[INDEX]], 3 |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = getelementptr nuw i8, ptr [[P]], i64 [[TMP23]] |
| ; CHECK-UF2-NEXT: [[TMP24:%.*]] = mul i64 [[TMP3]], 8 |
| ; CHECK-UF2-NEXT: [[TMP20:%.*]] = getelementptr nuw i8, ptr [[TMP18]], i64 [[TMP24]] |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP16]], ptr align 4 [[TMP18]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP21]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP17]], ptr align 4 [[TMP20]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP21]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[TMP8]], %[[MIDDLE_BLOCK]] ], [ [[P]], %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[PTR:%.*]] = phi ptr [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; CHECK-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; CHECK-UF2-NEXT: store i32 [[Y0]], ptr [[PTR]], align 4 |
| ; CHECK-UF2-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 8 |
| ; CHECK-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %ptr = phi ptr [%p, %entry], [%ptr.next, %loop] |
| |
| %x0 = load i32, ptr %ptr |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %ptr |
| |
| %ptr.next = getelementptr inbounds i8, ptr %ptr, i64 8 |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| |
| define void @single_stride_int_scaled(ptr %p, i64 %stride) { |
| ; NOSTRIDED-LABEL: define void @single_stride_int_scaled( |
| ; NOSTRIDED-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-NEXT: [[ENTRY:.*:]] |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED: [[VECTOR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED: [[VECTOR_BODY]]: |
| ; NOSTRIDED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; NOSTRIDED-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP10:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP10]], ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP11:%.*]] = zext i32 [[TMP7]] to i64 |
| ; NOSTRIDED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP11]], [[INDEX]] |
| ; NOSTRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]] |
| ; NOSTRIDED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; NOSTRIDED-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-NEXT: br label %[[EXIT:.*]] |
| ; NOSTRIDED: [[SCALAR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED: [[LOOP]]: |
| ; NOSTRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[EXIT]]: |
| ; NOSTRIDED-NEXT: ret void |
| ; |
| ; NOSTRIDED-UF2-LABEL: define void @single_stride_int_scaled( |
| ; NOSTRIDED-UF2-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; NOSTRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-UF2-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; NOSTRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; NOSTRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_BODY]]: |
| ; NOSTRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP4]], i64 [[TMP5]] |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[TMP8:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: [[TMP9:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD1]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP8]], ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP9]], ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; NOSTRIDED-UF2: [[SCALAR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; NOSTRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED-UF2: [[LOOP]]: |
| ; NOSTRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[EXIT]]: |
| ; NOSTRIDED-UF2-NEXT: ret void |
| ; |
| ; STRIDED-COMMON-LABEL: define void @single_stride_int_scaled( |
| ; STRIDED-COMMON-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; STRIDED-COMMON-NEXT: [[ENTRY:.*]]: |
| ; STRIDED-COMMON-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED-COMMON: [[LOOP]]: |
| ; STRIDED-COMMON-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-COMMON-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; STRIDED-COMMON-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-COMMON-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; STRIDED-COMMON-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-COMMON-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; STRIDED-COMMON-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-COMMON-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-COMMON-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; STRIDED-COMMON: [[EXIT]]: |
| ; STRIDED-COMMON-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| |
| %offset = mul nsw nuw i64 %i, %stride |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %q0 |
| |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @single_stride_int_iv(ptr %p, i64 %stride) { |
| ; NOSTRIDED-LABEL: define void @single_stride_int_iv( |
| ; NOSTRIDED-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-NEXT: [[ENTRY:.*:]] |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED: [[VECTOR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED: [[VECTOR_BODY]]: |
| ; NOSTRIDED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; NOSTRIDED-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP10:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP10]], ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP11:%.*]] = zext i32 [[TMP7]] to i64 |
| ; NOSTRIDED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP11]], [[INDEX]] |
| ; NOSTRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]] |
| ; NOSTRIDED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; NOSTRIDED-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-NEXT: br label %[[EXIT:.*]] |
| ; NOSTRIDED: [[SCALAR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED: [[LOOP]]: |
| ; NOSTRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[OFFSET:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[EXIT]]: |
| ; NOSTRIDED-NEXT: ret void |
| ; |
| ; NOSTRIDED-UF2-LABEL: define void @single_stride_int_iv( |
| ; NOSTRIDED-UF2-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; NOSTRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-UF2-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; NOSTRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; NOSTRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_BODY]]: |
| ; NOSTRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP4]], i64 [[TMP5]] |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[TMP8:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: [[TMP9:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD1]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP8]], ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP9]], ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; NOSTRIDED-UF2: [[SCALAR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; NOSTRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED-UF2: [[LOOP]]: |
| ; NOSTRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[EXIT]]: |
| ; NOSTRIDED-UF2-NEXT: ret void |
| ; |
| ; STRIDED-COMMON-LABEL: define void @single_stride_int_iv( |
| ; STRIDED-COMMON-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-COMMON-NEXT: [[ENTRY:.*]]: |
| ; STRIDED-COMMON-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED-COMMON: [[LOOP]]: |
| ; STRIDED-COMMON-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-COMMON-NEXT: [[OFFSET:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-COMMON-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-COMMON-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; STRIDED-COMMON-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-COMMON-NEXT: store i32 [[Y0]], ptr [[Q0]], align 4 |
| ; STRIDED-COMMON-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; STRIDED-COMMON-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-COMMON-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-COMMON-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; STRIDED-COMMON: [[EXIT]]: |
| ; STRIDED-COMMON-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %offset = phi i64 [0, %entry], [%offset.next, %loop] |
| |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %q0 |
| |
| %offset.next = add nsw nuw i64 %offset, %stride |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| |
| define void @single_stride_ptr_iv(ptr %p, i64 %stride) { |
| ; COMMON-LABEL: define void @single_stride_ptr_iv( |
| ; COMMON-SAME: ptr [[P:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; COMMON-NEXT: [[ENTRY:.*]]: |
| ; COMMON-NEXT: br label %[[LOOP:.*]] |
| ; COMMON: [[LOOP]]: |
| ; COMMON-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; COMMON-NEXT: [[PTR:%.*]] = phi ptr [ [[P]], %[[ENTRY]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; COMMON-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; COMMON-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; COMMON-NEXT: store i32 [[Y0]], ptr [[PTR]], align 4 |
| ; COMMON-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE]] |
| ; COMMON-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; COMMON-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; COMMON-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; COMMON: [[EXIT]]: |
| ; COMMON-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %ptr = phi ptr [%p, %entry], [%ptr.next, %loop] |
| |
| %x0 = load i32, ptr %ptr |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %ptr |
| |
| %ptr.next = getelementptr inbounds i8, ptr %ptr, i64 %stride |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) { |
| ; NOSTRIDED-LABEL: define void @double_stride_int_scaled( |
| ; NOSTRIDED-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-NEXT: [[ENTRY:.*:]] |
| ; NOSTRIDED-NEXT: [[P3:%.*]] = ptrtoaddr ptr [[P]] to i64 |
| ; NOSTRIDED-NEXT: [[P21:%.*]] = ptrtoaddr ptr [[P2]] to i64 |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] |
| ; NOSTRIDED: [[VECTOR_MEMCHECK]]: |
| ; NOSTRIDED-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-NEXT: [[TMP1:%.*]] = shl i64 [[TMP3]], 4 |
| ; NOSTRIDED-NEXT: [[TMP8:%.*]] = add i64 [[TMP1]], -1 |
| ; NOSTRIDED-NEXT: [[TMP6:%.*]] = sub i64 [[P21]], [[P3]] |
| ; NOSTRIDED-NEXT: [[TMP7:%.*]] = sub i64 [[TMP6]], 1 |
| ; NOSTRIDED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP7]], [[TMP8]] |
| ; NOSTRIDED-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED: [[VECTOR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED: [[VECTOR_BODY]]: |
| ; NOSTRIDED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[TMP16:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; NOSTRIDED-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]]) |
| ; NOSTRIDED-NEXT: [[TMP14:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[P2]], i64 [[INDEX]] |
| ; NOSTRIDED-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP14]], ptr align 4 [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]]) |
| ; NOSTRIDED-NEXT: [[TMP13:%.*]] = zext i32 [[TMP16]] to i64 |
| ; NOSTRIDED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP13]], [[INDEX]] |
| ; NOSTRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]] |
| ; NOSTRIDED-NEXT: [[TMP11:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; NOSTRIDED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-NEXT: br label %[[EXIT:.*]] |
| ; NOSTRIDED: [[SCALAR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED: [[LOOP]]: |
| ; NOSTRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P2]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; NOSTRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[EXIT]]: |
| ; NOSTRIDED-NEXT: ret void |
| ; |
| ; NOSTRIDED-UF2-LABEL: define void @double_stride_int_scaled( |
| ; NOSTRIDED-UF2-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-UF2-NEXT: [[P3:%.*]] = ptrtoaddr ptr [[P]] to i64 |
| ; NOSTRIDED-UF2-NEXT: [[P21:%.*]] = ptrtoaddr ptr [[P2]] to i64 |
| ; NOSTRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; NOSTRIDED-UF2-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 14) |
| ; NOSTRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[UMAX]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-UF2-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_MEMCHECK]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 5 |
| ; NOSTRIDED-UF2-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], -1 |
| ; NOSTRIDED-UF2-NEXT: [[TMP5:%.*]] = sub i64 [[P21]], [[P3]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP10:%.*]] = sub i64 [[TMP5]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP10]], [[TMP15]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; NOSTRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; NOSTRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_BODY]]: |
| ; NOSTRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-UF2-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i64 [[TMP9]] |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP8]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x i32>, ptr [[TMP11]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[TMP12:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: [[TMP13:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD4]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[P2]], i64 [[INDEX]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP14]], i64 [[TMP9]] |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP12]], ptr [[TMP14]], align 4 |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP13]], ptr [[TMP17]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; NOSTRIDED-UF2: [[SCALAR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ] |
| ; NOSTRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED-UF2: [[LOOP]]: |
| ; NOSTRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P2]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[EXIT]]: |
| ; NOSTRIDED-UF2-NEXT: ret void |
| ; |
| ; STRIDED-LABEL: define void @double_stride_int_scaled( |
| ; STRIDED-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-NEXT: [[ENTRY:.*:]] |
| ; STRIDED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] |
| ; STRIDED: [[VECTOR_SCEVCHECK]]: |
| ; STRIDED-NEXT: [[TMP24:%.*]] = shl i64 [[STRIDE]], 2 |
| ; STRIDED-NEXT: [[TMP25:%.*]] = mul i64 [[STRIDE]], -4 |
| ; STRIDED-NEXT: [[TMP26:%.*]] = icmp slt i64 [[TMP24]], 0 |
| ; STRIDED-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], i64 [[TMP25]], i64 [[TMP24]] |
| ; STRIDED-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[TMP27]], i64 1023) |
| ; STRIDED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0 |
| ; STRIDED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1 |
| ; STRIDED-NEXT: [[TMP28:%.*]] = sub i64 0, [[MUL_RESULT]] |
| ; STRIDED-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[P2]], i64 [[MUL_RESULT]] |
| ; STRIDED-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP28]] |
| ; STRIDED-NEXT: [[TMP31:%.*]] = icmp ult ptr [[TMP29]], [[P2]] |
| ; STRIDED-NEXT: [[TMP32:%.*]] = icmp ugt ptr [[TMP30]], [[P2]] |
| ; STRIDED-NEXT: [[TMP33:%.*]] = select i1 [[TMP26]], i1 [[TMP32]], i1 [[TMP31]] |
| ; STRIDED-NEXT: [[TMP13:%.*]] = or i1 [[TMP33]], [[MUL_OVERFLOW]] |
| ; STRIDED-NEXT: [[TMP34:%.*]] = icmp slt i64 [[TMP24]], 0 |
| ; STRIDED-NEXT: [[TMP15:%.*]] = select i1 [[TMP34]], i64 [[TMP25]], i64 [[TMP24]] |
| ; STRIDED-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[TMP15]], i64 1023) |
| ; STRIDED-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0 |
| ; STRIDED-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1 |
| ; STRIDED-NEXT: [[TMP16:%.*]] = sub i64 0, [[MUL_RESULT2]] |
| ; STRIDED-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT2]] |
| ; STRIDED-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP16]] |
| ; STRIDED-NEXT: [[TMP37:%.*]] = icmp ult ptr [[TMP35]], [[P]] |
| ; STRIDED-NEXT: [[TMP38:%.*]] = icmp ugt ptr [[TMP36]], [[P]] |
| ; STRIDED-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i1 [[TMP38]], i1 [[TMP37]] |
| ; STRIDED-NEXT: [[TMP40:%.*]] = or i1 [[TMP39]], [[MUL_OVERFLOW3]] |
| ; STRIDED-NEXT: [[TMP23:%.*]] = or i1 [[TMP13]], [[TMP40]] |
| ; STRIDED-NEXT: br i1 [[TMP23]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] |
| ; STRIDED: [[VECTOR_MEMCHECK]]: |
| ; STRIDED-NEXT: [[TMP3:%.*]] = mul i64 [[STRIDE]], 4092 |
| ; STRIDED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP3]] |
| ; STRIDED-NEXT: [[TMP4:%.*]] = icmp ult ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-NEXT: [[UMIN:%.*]] = select i1 [[TMP4]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-NEXT: [[TMP5:%.*]] = icmp ugt ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-NEXT: [[UMAX:%.*]] = select i1 [[TMP5]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[UMAX]], i64 4 |
| ; STRIDED-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP3]] |
| ; STRIDED-NEXT: [[TMP6:%.*]] = icmp ult ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[UMIN3:%.*]] = select i1 [[TMP6]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[TMP7:%.*]] = icmp ugt ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[UMAX4:%.*]] = select i1 [[TMP7]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[UMAX4]], i64 4 |
| ; STRIDED-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[UMIN]], [[SCEVGEP5]] |
| ; STRIDED-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[UMIN3]], [[SCEVGEP1]] |
| ; STRIDED-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; STRIDED-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; STRIDED: [[VECTOR_PH]]: |
| ; STRIDED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0 |
| ; STRIDED-NEXT: [[BROADCAST_SPLAT1:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-NEXT: [[TMP12:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; STRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; STRIDED: [[VECTOR_BODY]]: |
| ; STRIDED-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP12]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-NEXT: [[TMP43:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; STRIDED-NEXT: [[TMP44:%.*]] = zext i32 [[TMP43]] to i64 |
| ; STRIDED-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP44]], i64 0 |
| ; STRIDED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT9]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-NEXT: [[TMP18:%.*]] = mul nuw nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT1]] |
| ; STRIDED-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[P]], <vscale x 4 x i64> [[TMP18]] |
| ; STRIDED-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[TMP19]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP43]]), !alias.scope [[META5:![0-9]+]] |
| ; STRIDED-NEXT: [[TMP20:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; STRIDED-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[P2]], <vscale x 4 x i64> [[TMP18]] |
| ; STRIDED-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP20]], <vscale x 4 x ptr> align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP43]]), !alias.scope [[META8:![0-9]+]], !noalias [[META5]] |
| ; STRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP44]] |
| ; STRIDED-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] |
| ; STRIDED-NEXT: [[TMP41:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; STRIDED-NEXT: br i1 [[TMP41]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED: [[MIDDLE_BLOCK]]: |
| ; STRIDED-NEXT: br label %[[EXIT:.*]] |
| ; STRIDED: [[SCALAR_PH]]: |
| ; STRIDED-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED: [[LOOP]]: |
| ; STRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; STRIDED-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; STRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P2]], i64 [[OFFSET]] |
| ; STRIDED-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; STRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED: [[EXIT]]: |
| ; STRIDED-NEXT: ret void |
| ; |
| ; STRIDED-UF2-LABEL: define void @double_stride_int_scaled( |
| ; STRIDED-UF2-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; STRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; STRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; STRIDED-UF2-NEXT: [[UMAX9:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 79) |
| ; STRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[UMAX9]] |
| ; STRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; STRIDED-UF2: [[VECTOR_SCEVCHECK]]: |
| ; STRIDED-UF2-NEXT: [[TMP2:%.*]] = shl i64 [[STRIDE]], 2 |
| ; STRIDED-UF2-NEXT: [[TMP3:%.*]] = mul i64 [[STRIDE]], -4 |
| ; STRIDED-UF2-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP2]], 0 |
| ; STRIDED-UF2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP3]], i64 [[TMP2]] |
| ; STRIDED-UF2-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[TMP5]], i64 1023) |
| ; STRIDED-UF2-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0 |
| ; STRIDED-UF2-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1 |
| ; STRIDED-UF2-NEXT: [[TMP6:%.*]] = sub i64 0, [[MUL_RESULT]] |
| ; STRIDED-UF2-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P2]], i64 [[MUL_RESULT]] |
| ; STRIDED-UF2-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP6]] |
| ; STRIDED-UF2-NEXT: [[TMP9:%.*]] = icmp ult ptr [[TMP7]], [[P2]] |
| ; STRIDED-UF2-NEXT: [[TMP10:%.*]] = icmp ugt ptr [[TMP8]], [[P2]] |
| ; STRIDED-UF2-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i1 [[TMP10]], i1 [[TMP9]] |
| ; STRIDED-UF2-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]] |
| ; STRIDED-UF2-NEXT: [[TMP13:%.*]] = icmp slt i64 [[TMP2]], 0 |
| ; STRIDED-UF2-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i64 [[TMP3]], i64 [[TMP2]] |
| ; STRIDED-UF2-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[TMP14]], i64 1023) |
| ; STRIDED-UF2-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0 |
| ; STRIDED-UF2-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1 |
| ; STRIDED-UF2-NEXT: [[TMP15:%.*]] = sub i64 0, [[MUL_RESULT2]] |
| ; STRIDED-UF2-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT2]] |
| ; STRIDED-UF2-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP15]] |
| ; STRIDED-UF2-NEXT: [[TMP18:%.*]] = icmp ult ptr [[TMP16]], [[P]] |
| ; STRIDED-UF2-NEXT: [[TMP19:%.*]] = icmp ugt ptr [[TMP17]], [[P]] |
| ; STRIDED-UF2-NEXT: [[TMP20:%.*]] = select i1 [[TMP13]], i1 [[TMP19]], i1 [[TMP18]] |
| ; STRIDED-UF2-NEXT: [[TMP21:%.*]] = or i1 [[TMP20]], [[MUL_OVERFLOW3]] |
| ; STRIDED-UF2-NEXT: [[TMP22:%.*]] = or i1 [[TMP12]], [[TMP21]] |
| ; STRIDED-UF2-NEXT: br i1 [[TMP22]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]] |
| ; STRIDED-UF2: [[VECTOR_MEMCHECK]]: |
| ; STRIDED-UF2-NEXT: [[TMP23:%.*]] = mul i64 [[STRIDE]], 4092 |
| ; STRIDED-UF2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP23]] |
| ; STRIDED-UF2-NEXT: [[TMP24:%.*]] = icmp ult ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[UMIN:%.*]] = select i1 [[TMP24]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[TMP25:%.*]] = icmp ugt ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[UMAX:%.*]] = select i1 [[TMP25]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[UMAX]], i64 4 |
| ; STRIDED-UF2-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP23]] |
| ; STRIDED-UF2-NEXT: [[TMP26:%.*]] = icmp ult ptr [[P]], [[SCEVGEP5]] |
| ; STRIDED-UF2-NEXT: [[UMIN6:%.*]] = select i1 [[TMP26]], ptr [[P]], ptr [[SCEVGEP5]] |
| ; STRIDED-UF2-NEXT: [[TMP27:%.*]] = icmp ugt ptr [[P]], [[SCEVGEP5]] |
| ; STRIDED-UF2-NEXT: [[UMAX7:%.*]] = select i1 [[TMP27]], ptr [[P]], ptr [[SCEVGEP5]] |
| ; STRIDED-UF2-NEXT: [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[UMAX7]], i64 4 |
| ; STRIDED-UF2-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[UMIN]], [[SCEVGEP8]] |
| ; STRIDED-UF2-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[UMIN6]], [[SCEVGEP4]] |
| ; STRIDED-UF2-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; STRIDED-UF2-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; STRIDED-UF2: [[VECTOR_PH]]: |
| ; STRIDED-UF2-NEXT: [[TMP29:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP29]], i64 0 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; STRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT10]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-UF2-NEXT: [[TMP31:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; STRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; STRIDED-UF2: [[VECTOR_BODY]]: |
| ; STRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-UF2-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP31]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-UF2-NEXT: [[STEP_ADD:%.*]] = add nuw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] |
| ; STRIDED-UF2-NEXT: [[TMP33:%.*]] = mul nuw nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT11]] |
| ; STRIDED-UF2-NEXT: [[TMP34:%.*]] = mul nuw nsw <vscale x 4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT11]] |
| ; STRIDED-UF2-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[P]], <vscale x 4 x i64> [[TMP33]] |
| ; STRIDED-UF2-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[P]], <vscale x 4 x i64> [[TMP34]] |
| ; STRIDED-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[TMP35]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison), !alias.scope [[META8:![0-9]+]] |
| ; STRIDED-UF2-NEXT: [[WIDE_MASKED_GATHER12:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[TMP36]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison), !alias.scope [[META8]] |
| ; STRIDED-UF2-NEXT: [[TMP37:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; STRIDED-UF2-NEXT: [[TMP38:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER12]], splat (i32 1) |
| ; STRIDED-UF2-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[P2]], <vscale x 4 x i64> [[TMP33]] |
| ; STRIDED-UF2-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr [[P2]], <vscale x 4 x i64> [[TMP34]] |
| ; STRIDED-UF2-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP37]], <vscale x 4 x ptr> align 4 [[TMP39]], <vscale x 4 x i1> splat (i1 true)), !alias.scope [[META11:![0-9]+]], !noalias [[META8]] |
| ; STRIDED-UF2-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP38]], <vscale x 4 x ptr> align 4 [[TMP40]], <vscale x 4 x i1> splat (i1 true)), !alias.scope [[META11]], !noalias [[META8]] |
| ; STRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; STRIDED-UF2-NEXT: [[VEC_IND_NEXT]] = add <vscale x 4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]] |
| ; STRIDED-UF2-NEXT: [[TMP41:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; STRIDED-UF2-NEXT: br i1 [[TMP41]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; STRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; STRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; STRIDED-UF2: [[SCALAR_PH]]: |
| ; STRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ], [ 0, %[[VECTOR_MEMCHECK]] ] |
| ; STRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED-UF2: [[LOOP]]: |
| ; STRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-UF2-NEXT: [[OFFSET:%.*]] = mul nuw nsw i64 [[I]], [[STRIDE]] |
| ; STRIDED-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; STRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-UF2-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P2]], i64 [[OFFSET]] |
| ; STRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; STRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED-UF2: [[EXIT]]: |
| ; STRIDED-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| |
| %offset = mul nsw nuw i64 %i, %stride |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| %q1 = getelementptr i32, ptr %p2, i64 %offset |
| store i32 %y0, ptr %q1 |
| |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @double_stride_int_iv(ptr %p, ptr %p2, i64 %stride) { |
| ; NOSTRIDED-LABEL: define void @double_stride_int_iv( |
| ; NOSTRIDED-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-NEXT: [[ENTRY:.*:]] |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED: [[VECTOR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED: [[VECTOR_BODY]]: |
| ; NOSTRIDED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; NOSTRIDED-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 4 x i32> @llvm.vp.load.nxv4i32.p0(ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP10:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP10]], ptr align 4 [[TMP8]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; NOSTRIDED-NEXT: [[TMP11:%.*]] = zext i32 [[TMP7]] to i64 |
| ; NOSTRIDED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP11]], [[INDEX]] |
| ; NOSTRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP11]] |
| ; NOSTRIDED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; NOSTRIDED-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-NEXT: br label %[[EXIT:.*]] |
| ; NOSTRIDED: [[SCALAR_PH]]: |
| ; NOSTRIDED-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED: [[LOOP]]: |
| ; NOSTRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[OFFSET:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; NOSTRIDED-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED: [[EXIT]]: |
| ; NOSTRIDED-NEXT: ret void |
| ; |
| ; NOSTRIDED-UF2-LABEL: define void @double_stride_int_iv( |
| ; NOSTRIDED-UF2-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; NOSTRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; NOSTRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_SCEVCHECK]]: |
| ; NOSTRIDED-UF2-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[STRIDE]], 1 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; NOSTRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; NOSTRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NOSTRIDED-UF2: [[VECTOR_BODY]]: |
| ; NOSTRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NOSTRIDED-UF2-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[P]], i64 [[INDEX]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP4]], i64 [[TMP5]] |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x i32>, ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[TMP8:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: [[TMP9:%.*]] = add <vscale x 4 x i32> [[WIDE_LOAD1]], splat (i32 1) |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP8]], ptr [[TMP4]], align 4 |
| ; NOSTRIDED-UF2-NEXT: store <vscale x 4 x i32> [[TMP9]], ptr [[TMP7]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; NOSTRIDED-UF2-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; NOSTRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; NOSTRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; NOSTRIDED-UF2: [[SCALAR_PH]]: |
| ; NOSTRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; NOSTRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED-UF2: [[LOOP]]: |
| ; NOSTRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; NOSTRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; NOSTRIDED-UF2: [[EXIT]]: |
| ; NOSTRIDED-UF2-NEXT: ret void |
| ; |
| ; STRIDED-COMMON-LABEL: define void @double_stride_int_iv( |
| ; STRIDED-COMMON-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-COMMON-NEXT: [[ENTRY:.*]]: |
| ; STRIDED-COMMON-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED-COMMON: [[LOOP]]: |
| ; STRIDED-COMMON-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-COMMON-NEXT: [[OFFSET:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OFFSET_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-COMMON-NEXT: [[Q0:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-COMMON-NEXT: [[X0:%.*]] = load i32, ptr [[Q0]], align 4 |
| ; STRIDED-COMMON-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-COMMON-NEXT: [[Q1:%.*]] = getelementptr i32, ptr [[P]], i64 [[OFFSET]] |
| ; STRIDED-COMMON-NEXT: store i32 [[Y0]], ptr [[Q1]], align 4 |
| ; STRIDED-COMMON-NEXT: [[OFFSET_NEXT]] = add nuw nsw i64 [[OFFSET]], [[STRIDE]] |
| ; STRIDED-COMMON-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-COMMON-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-COMMON-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; STRIDED-COMMON: [[EXIT]]: |
| ; STRIDED-COMMON-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %offset = phi i64 [0, %entry], [%offset.next, %loop] |
| |
| %q0 = getelementptr i32, ptr %p, i64 %offset |
| %x0 = load i32, ptr %q0 |
| %y0 = add i32 %x0, 1 |
| %q1 = getelementptr i32, ptr %p, i64 %offset |
| store i32 %y0, ptr %q1 |
| |
| %offset.next = add nsw nuw i64 %offset, %stride |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| define void @double_stride_ptr_iv(ptr %p, ptr %p2, i64 %stride) { |
| ; NOSTRIDED-LABEL: define void @double_stride_ptr_iv( |
| ; NOSTRIDED-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED: [[LOOP]]: |
| ; NOSTRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[PTR:%.*]] = phi ptr [ [[P]], %[[ENTRY]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[PTR2:%.*]] = phi ptr [ [[P2]], %[[ENTRY]] ], [ [[PTR2_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; NOSTRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-NEXT: store i32 [[Y0]], ptr [[PTR2]], align 4 |
| ; NOSTRIDED-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[PTR2_NEXT]] = getelementptr inbounds i8, ptr [[PTR2]], i64 [[STRIDE]] |
| ; NOSTRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; NOSTRIDED: [[EXIT]]: |
| ; NOSTRIDED-NEXT: ret void |
| ; |
| ; NOSTRIDED-UF2-LABEL: define void @double_stride_ptr_iv( |
| ; NOSTRIDED-UF2-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; NOSTRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; NOSTRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; NOSTRIDED-UF2: [[LOOP]]: |
| ; NOSTRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[PTR:%.*]] = phi ptr [ [[P]], %[[ENTRY]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[PTR2:%.*]] = phi ptr [ [[P2]], %[[ENTRY]] ], [ [[PTR2_NEXT:%.*]], %[[LOOP]] ] |
| ; NOSTRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; NOSTRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[PTR2]], align 4 |
| ; NOSTRIDED-UF2-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[PTR2_NEXT]] = getelementptr inbounds i8, ptr [[PTR2]], i64 [[STRIDE]] |
| ; NOSTRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; NOSTRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; NOSTRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]] |
| ; NOSTRIDED-UF2: [[EXIT]]: |
| ; NOSTRIDED-UF2-NEXT: ret void |
| ; |
| ; STRIDED-LABEL: define void @double_stride_ptr_iv( |
| ; STRIDED-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-NEXT: [[ENTRY:.*:]] |
| ; STRIDED-NEXT: br label %[[VECTOR_MEMCHECK:.*]] |
| ; STRIDED: [[VECTOR_MEMCHECK]]: |
| ; STRIDED-NEXT: [[TMP3:%.*]] = mul i64 [[STRIDE]], 1023 |
| ; STRIDED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP3]] |
| ; STRIDED-NEXT: [[TMP4:%.*]] = icmp ult ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-NEXT: [[UMIN:%.*]] = select i1 [[TMP4]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-NEXT: [[TMP5:%.*]] = icmp ugt ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-NEXT: [[UMAX:%.*]] = select i1 [[TMP5]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[UMAX]], i64 4 |
| ; STRIDED-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP3]] |
| ; STRIDED-NEXT: [[TMP6:%.*]] = icmp ult ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[UMIN3:%.*]] = select i1 [[TMP6]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[TMP7:%.*]] = icmp ugt ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[UMAX4:%.*]] = select i1 [[TMP7]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[UMAX4]], i64 4 |
| ; STRIDED-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[UMIN]], [[SCEVGEP5]] |
| ; STRIDED-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[UMIN3]], [[SCEVGEP1]] |
| ; STRIDED-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; STRIDED-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; STRIDED: [[VECTOR_PH]]: |
| ; STRIDED-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; STRIDED: [[VECTOR_BODY]]: |
| ; STRIDED-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], %[[VECTOR_PH]] ], [ [[PTR_IND:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-NEXT: [[POINTER_PHI11:%.*]] = phi ptr [ [[P2]], %[[VECTOR_PH]] ], [ [[PTR_IND12:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-NEXT: [[TMP19:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; STRIDED-NEXT: [[DOTSPLATINSERT9:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0 |
| ; STRIDED-NEXT: [[DOTSPLAT10:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT9]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-NEXT: [[TMP18:%.*]] = mul <vscale x 4 x i64> [[TMP19]], [[DOTSPLAT10]] |
| ; STRIDED-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI11]], <vscale x 4 x i64> [[TMP18]] |
| ; STRIDED-NEXT: [[VECTOR_GEP7:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 4 x i64> [[TMP18]] |
| ; STRIDED-NEXT: [[TMP14:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; STRIDED-NEXT: [[TMP16:%.*]] = zext i32 [[TMP14]] to i64 |
| ; STRIDED-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[VECTOR_GEP7]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP14]]), !alias.scope [[META12:![0-9]+]] |
| ; STRIDED-NEXT: [[TMP9:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; STRIDED-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP9]], <vscale x 4 x ptr> align 4 [[VECTOR_GEP]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP14]]), !alias.scope [[META15:![0-9]+]], !noalias [[META12]] |
| ; STRIDED-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP16]] |
| ; STRIDED-NEXT: [[TMP25:%.*]] = mul i64 [[STRIDE]], [[TMP16]] |
| ; STRIDED-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP25]] |
| ; STRIDED-NEXT: [[PTR_IND12]] = getelementptr i8, ptr [[POINTER_PHI11]], i64 [[TMP25]] |
| ; STRIDED-NEXT: [[TMP23:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; STRIDED-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED: [[MIDDLE_BLOCK]]: |
| ; STRIDED-NEXT: br label %[[EXIT:.*]] |
| ; STRIDED: [[SCALAR_PH]]: |
| ; STRIDED-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED: [[LOOP]]: |
| ; STRIDED-NEXT: [[I:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-NEXT: [[PTR:%.*]] = phi ptr [ [[P]], %[[SCALAR_PH]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-NEXT: [[PTR2:%.*]] = phi ptr [ [[P2]], %[[SCALAR_PH]] ], [ [[PTR2_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; STRIDED-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-NEXT: store i32 [[Y0]], ptr [[PTR2]], align 4 |
| ; STRIDED-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE]] |
| ; STRIDED-NEXT: [[PTR2_NEXT]] = getelementptr inbounds i8, ptr [[PTR2]], i64 [[STRIDE]] |
| ; STRIDED-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED: [[EXIT]]: |
| ; STRIDED-NEXT: ret void |
| ; |
| ; STRIDED-UF2-LABEL: define void @double_stride_ptr_iv( |
| ; STRIDED-UF2-SAME: ptr [[P:%.*]], ptr [[P2:%.*]], i64 [[STRIDE:%.*]]) #[[ATTR0]] { |
| ; STRIDED-UF2-NEXT: [[ENTRY:.*]]: |
| ; STRIDED-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; STRIDED-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; STRIDED-UF2-NEXT: [[UMAX6:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 28) |
| ; STRIDED-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[UMAX6]] |
| ; STRIDED-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]] |
| ; STRIDED-UF2: [[VECTOR_MEMCHECK]]: |
| ; STRIDED-UF2-NEXT: [[TMP2:%.*]] = mul i64 [[STRIDE]], 1023 |
| ; STRIDED-UF2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP2]] |
| ; STRIDED-UF2-NEXT: [[TMP3:%.*]] = icmp ult ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[UMIN:%.*]] = select i1 [[TMP3]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[TMP4:%.*]] = icmp ugt ptr [[P2]], [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[UMAX:%.*]] = select i1 [[TMP4]], ptr [[P2]], ptr [[SCEVGEP]] |
| ; STRIDED-UF2-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[UMAX]], i64 4 |
| ; STRIDED-UF2-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP2]] |
| ; STRIDED-UF2-NEXT: [[TMP5:%.*]] = icmp ult ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-UF2-NEXT: [[UMIN3:%.*]] = select i1 [[TMP5]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-UF2-NEXT: [[TMP6:%.*]] = icmp ugt ptr [[P]], [[SCEVGEP2]] |
| ; STRIDED-UF2-NEXT: [[UMAX4:%.*]] = select i1 [[TMP6]], ptr [[P]], ptr [[SCEVGEP2]] |
| ; STRIDED-UF2-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[UMAX4]], i64 4 |
| ; STRIDED-UF2-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[UMIN]], [[SCEVGEP5]] |
| ; STRIDED-UF2-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[UMIN3]], [[SCEVGEP1]] |
| ; STRIDED-UF2-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; STRIDED-UF2-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; STRIDED-UF2: [[VECTOR_PH]]: |
| ; STRIDED-UF2-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP8]], i64 0 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; STRIDED-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT7]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-UF2-NEXT: [[TMP10:%.*]] = mul i64 [[N_VEC]], [[STRIDE]] |
| ; STRIDED-UF2-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP10]] |
| ; STRIDED-UF2-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP10]] |
| ; STRIDED-UF2-NEXT: [[TMP14:%.*]] = mul <vscale x 4 x i64> [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT8]] |
| ; STRIDED-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; STRIDED-UF2: [[VECTOR_BODY]]: |
| ; STRIDED-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-UF2-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], %[[VECTOR_PH]] ], [ [[PTR_IND:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-UF2-NEXT: [[POINTER_PHI9:%.*]] = phi ptr [ [[P2]], %[[VECTOR_PH]] ], [ [[PTR_IND15:%.*]], %[[VECTOR_BODY]] ] |
| ; STRIDED-UF2-NEXT: [[TMP15:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[STRIDE]], i64 0 |
| ; STRIDED-UF2-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT10]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; STRIDED-UF2-NEXT: [[TMP16:%.*]] = mul <vscale x 4 x i64> [[TMP15]], [[BROADCAST_SPLAT11]] |
| ; STRIDED-UF2-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI9]], <vscale x 4 x i64> [[TMP16]] |
| ; STRIDED-UF2-NEXT: [[VECTOR_GEP12:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 4 x i64> [[TMP16]] |
| ; STRIDED-UF2-NEXT: [[STEP_ADD:%.*]] = getelementptr i8, <vscale x 4 x ptr> [[VECTOR_GEP12]], <vscale x 4 x i64> [[TMP14]] |
| ; STRIDED-UF2-NEXT: [[STEP_ADD13:%.*]] = getelementptr i8, <vscale x 4 x ptr> [[VECTOR_GEP]], <vscale x 4 x i64> [[TMP14]] |
| ; STRIDED-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[VECTOR_GEP12]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison), !alias.scope [[META15:![0-9]+]] |
| ; STRIDED-UF2-NEXT: [[WIDE_MASKED_GATHER14:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[STEP_ADD]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison), !alias.scope [[META15]] |
| ; STRIDED-UF2-NEXT: [[TMP19:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER]], splat (i32 1) |
| ; STRIDED-UF2-NEXT: [[TMP20:%.*]] = add <vscale x 4 x i32> [[WIDE_MASKED_GATHER14]], splat (i32 1) |
| ; STRIDED-UF2-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP19]], <vscale x 4 x ptr> align 4 [[VECTOR_GEP]], <vscale x 4 x i1> splat (i1 true)), !alias.scope [[META18:![0-9]+]], !noalias [[META15]] |
| ; STRIDED-UF2-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> [[TMP20]], <vscale x 4 x ptr> align 4 [[STEP_ADD13]], <vscale x 4 x i1> splat (i1 true)), !alias.scope [[META18]], !noalias [[META15]] |
| ; STRIDED-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; STRIDED-UF2-NEXT: [[TMP21:%.*]] = mul i64 [[STRIDE]], [[TMP1]] |
| ; STRIDED-UF2-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 [[TMP21]] |
| ; STRIDED-UF2-NEXT: [[PTR_IND15]] = getelementptr i8, ptr [[POINTER_PHI9]], i64 [[TMP21]] |
| ; STRIDED-UF2-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; STRIDED-UF2-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED-UF2: [[MIDDLE_BLOCK]]: |
| ; STRIDED-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; STRIDED-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; STRIDED-UF2: [[SCALAR_PH]]: |
| ; STRIDED-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ] |
| ; STRIDED-UF2-NEXT: [[BC_RESUME_VAL15:%.*]] = phi ptr [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ [[P]], %[[ENTRY]] ], [ [[P]], %[[VECTOR_MEMCHECK]] ] |
| ; STRIDED-UF2-NEXT: [[BC_RESUME_VAL16:%.*]] = phi ptr [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ [[P2]], %[[ENTRY]] ], [ [[P2]], %[[VECTOR_MEMCHECK]] ] |
| ; STRIDED-UF2-NEXT: br label %[[LOOP:.*]] |
| ; STRIDED-UF2: [[LOOP]]: |
| ; STRIDED-UF2-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[NEXTI:%.*]], %[[LOOP]] ] |
| ; STRIDED-UF2-NEXT: [[PTR:%.*]] = phi ptr [ [[BC_RESUME_VAL15]], %[[SCALAR_PH]] ], [ [[PTR_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-UF2-NEXT: [[PTR2:%.*]] = phi ptr [ [[BC_RESUME_VAL16]], %[[SCALAR_PH]] ], [ [[PTR2_NEXT:%.*]], %[[LOOP]] ] |
| ; STRIDED-UF2-NEXT: [[X0:%.*]] = load i32, ptr [[PTR]], align 4 |
| ; STRIDED-UF2-NEXT: [[Y0:%.*]] = add i32 [[X0]], 1 |
| ; STRIDED-UF2-NEXT: store i32 [[Y0]], ptr [[PTR2]], align 4 |
| ; STRIDED-UF2-NEXT: [[PTR_NEXT]] = getelementptr inbounds i8, ptr [[PTR]], i64 [[STRIDE]] |
| ; STRIDED-UF2-NEXT: [[PTR2_NEXT]] = getelementptr inbounds i8, ptr [[PTR2]], i64 [[STRIDE]] |
| ; STRIDED-UF2-NEXT: [[NEXTI]] = add i64 [[I]], 1 |
| ; STRIDED-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[NEXTI]], 1024 |
| ; STRIDED-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; STRIDED-UF2: [[EXIT]]: |
| ; STRIDED-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| loop: |
| %i = phi i64 [0, %entry], [%nexti, %loop] |
| %ptr = phi ptr [%p, %entry], [%ptr.next, %loop] |
| %ptr2 = phi ptr [%p2, %entry], [%ptr2.next, %loop] |
| |
| %x0 = load i32, ptr %ptr |
| %y0 = add i32 %x0, 1 |
| store i32 %y0, ptr %ptr2 |
| |
| %ptr.next = getelementptr inbounds i8, ptr %ptr, i64 %stride |
| %ptr2.next = getelementptr inbounds i8, ptr %ptr2, i64 %stride |
| %nexti = add i64 %i, 1 |
| %done = icmp eq i64 %nexti, 1024 |
| br i1 %done, label %exit, label %loop |
| exit: |
| ret void |
| } |
| |
| ; |
| ; The %in pointer strides in 32-bit steps, but the load accesses in 64-bit. |
| ; This checks handling of mismatched stride and access size. |
| ; |
| ; void reinterpret(int32_t* in, int64_t* out) { |
| ; for (unsigned i = 0; i < 1024; i++) { |
| ; int64_t val = *reinterpret_cast<int64_t*>(&in[i]); |
| ; out[i] = val; |
| ; } |
| ; } |
| ; |
| define void @constant_stride_reinterpret(ptr noalias %in, ptr noalias %out) { |
| ; CHECK-LABEL: define void @constant_stride_reinterpret( |
| ; CHECK-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true) |
| ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr nuw i8, ptr [[IN]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64.p0.i64(ptr align 8 [[TMP6]], i64 4, <vscale x 2 x i1> splat (i1 true), i32 [[TMP1]]) |
| ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i64, ptr [[OUT]], i64 [[INDEX]] |
| ; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[WIDE_MASKED_GATHER]], ptr align 8 [[TMP4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP1]]) |
| ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP2]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @constant_stride_reinterpret( |
| ; CHECK-UF2-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 1 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP3]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = shl nuw i64 [[INDEX]], 2 |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = getelementptr nuw i8, ptr [[IN]], i64 [[TMP5]] |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP3]], 4 |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = getelementptr nuw i8, ptr [[TMP6]], i64 [[TMP7]] |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64.p0.i64(ptr align 8 [[TMP6]], i64 4, <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]) |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER1:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64.p0.i64(ptr align 8 [[TMP13]], i64 4, <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]) |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i64, ptr [[OUT]], i64 [[INDEX]] |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw i64, ptr [[TMP8]], i64 [[TMP3]] |
| ; CHECK-UF2-NEXT: store <vscale x 2 x i64> [[WIDE_MASKED_GATHER]], ptr [[TMP8]], align 8 |
| ; CHECK-UF2-NEXT: store <vscale x 2 x i64> [[WIDE_MASKED_GATHER1]], ptr [[TMP9]], align 8 |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[IN]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i64, ptr [[OUT]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: store i64 [[TMP11]], ptr [[ARRAYIDX2]], align 8 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %arrayidx = getelementptr inbounds nuw i32, ptr %in, i64 %iv |
| %0 = load i64, ptr %arrayidx, align 8 |
| %arrayidx2 = getelementptr inbounds nuw i64, ptr %out, i64 %iv |
| store i64 %0, ptr %arrayidx2, align 8 |
| %iv.next = add nuw nsw i64 %iv, 1 |
| %done = icmp eq i64 %iv.next, 1024 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| ; Check that an access pattern matching as both an interleave group and a |
| ; strided access at the same time is vectorized as an interleaved load rather |
| ; than a strided load. |
| define void @interleaved_load_instead_of_strided(ptr %a) { |
| ; CHECK-LABEL: define void @interleaved_load_instead_of_strided( |
| ; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP0]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP2]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [4 x i32], ptr [[A]], <vscale x 4 x i64> [[VEC_IND]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <vscale x 4 x ptr> [[TMP3]], i64 0 |
| ; CHECK-NEXT: [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP1]], 4 |
| ; CHECK-NEXT: [[WIDE_VP_LOAD:%.*]] = call <vscale x 16 x i32> @llvm.vp.load.nxv16i32.p0(ptr align 4 [[TMP4]], <vscale x 16 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]]) |
| ; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave4.nxv16i32(<vscale x 16 x i32> [[WIDE_VP_LOAD]]) |
| ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 1 |
| ; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 3 |
| ; CHECK-NEXT: [[TMP8:%.*]] = add <vscale x 4 x i32> [[TMP5]], [[TMP6]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = add <vscale x 4 x i32> [[TMP8]], [[TMP7]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP11]] |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP9]], ptr align 4 [[TMP12]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP1]]) |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP2]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP2]] |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @interleaved_load_instead_of_strided( |
| ; CHECK-UF2-SAME: ptr [[A:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP3]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP3]] to i32 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP5]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[STEP_ADD:%.*]] = add nuw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = getelementptr [4 x i32], ptr [[A]], <vscale x 4 x i64> [[VEC_IND]] |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = getelementptr [4 x i32], ptr [[A]], <vscale x 4 x i64> [[STEP_ADD]] |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = extractelement <vscale x 4 x ptr> [[TMP6]], i64 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 16 x i32>, ptr [[TMP7]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave4.nxv16i32(<vscale x 16 x i32> [[WIDE_VEC]]) |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 1 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 3 |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = extractelement <vscale x 4 x ptr> [[TMP8]], i64 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC1:%.*]] = load <vscale x 16 x i32>, ptr [[TMP9]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC2:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave4.nxv16i32(<vscale x 16 x i32> [[WIDE_VEC1]]) |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 1 |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 3 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = add <vscale x 4 x i32> [[TMP10]], [[TMP11]] |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = add <vscale x 4 x i32> [[TMP13]], [[TMP14]] |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = add <vscale x 4 x i32> [[TMP16]], [[TMP12]] |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = add <vscale x 4 x i32> [[TMP17]], [[TMP15]] |
| ; CHECK-UF2-NEXT: [[TMP23:%.*]] = shl i64 [[INDEX]], 4 |
| ; CHECK-UF2-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP23]] |
| ; CHECK-UF2-NEXT: [[TMP25:%.*]] = mul i64 [[TMP3]], 16 |
| ; CHECK-UF2-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[TMP24]], i64 [[TMP25]] |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP18]], ptr align 4 [[TMP24]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP22]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP19]], ptr align 4 [[TMP21]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP22]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <vscale x 4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]] |
| ; CHECK-UF2-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[BASE:%.*]] = getelementptr [4 x i32], ptr [[A]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: [[V0:%.*]] = load i32, ptr [[BASE]], align 4 |
| ; CHECK-UF2-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[BASE]], i64 4 |
| ; CHECK-UF2-NEXT: [[V1:%.*]] = load i32, ptr [[P1]], align 4 |
| ; CHECK-UF2-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[BASE]], i64 12 |
| ; CHECK-UF2-NEXT: [[V3:%.*]] = load i32, ptr [[P3]], align 4 |
| ; CHECK-UF2-NEXT: [[ADD0:%.*]] = add i32 [[V0]], [[V1]] |
| ; CHECK-UF2-NEXT: [[ADD1:%.*]] = add i32 [[ADD0]], [[V3]] |
| ; CHECK-UF2-NEXT: store i32 [[ADD1]], ptr [[BASE]], align 4 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %base = getelementptr [4 x i32], ptr %a, i64 %iv |
| %v0 = load i32, ptr %base, align 4 |
| %p1 = getelementptr i8, ptr %base, i64 4 |
| %v1 = load i32, ptr %p1, align 4 |
| %p3 = getelementptr i8, ptr %base, i64 12 |
| %v3 = load i32, ptr %p3, align 4 |
| %add0 = add i32 %v0, %v1 |
| %add1 = add i32 %add0, %v3 |
| store i32 %add1, ptr %base, align 4 |
| %iv.next = add nuw nsw i64 %iv, 1 |
| %done = icmp eq i64 %iv.next, 1024 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| ; VPTypeAnalysis issue: crash in convertToStridedAccesses due to stale cache. |
| define void @type_cache_crash(ptr noalias %a, ptr noalias %b, ptr noalias %c, i32 %n, double %c0, double %c1, double %c2, i64 %c3) { |
| ; CHECK-LABEL: define void @type_cache_crash( |
| ; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i32 [[N:%.*]], double [[C0:%.*]], double [[C1:%.*]], double [[C2:%.*]], i64 [[C3:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 4) |
| ; CHECK-NEXT: [[TMP0:%.*]] = add nsw i32 [[SMAX]], -1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1 |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x double> poison, double [[C0]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP3:%.*]] = fneg <vscale x 2 x double> [[BROADCAST_SPLAT]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = fsub double 0.000000e+00, [[C1]] |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP4]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT7]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[C3]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i64 48 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x double> poison, double [[C2]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[C]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x ptr> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x ptr> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ [[TMP2]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 2, i1 true) |
| ; CHECK-NEXT: store double 0.000000e+00, ptr [[A]], align 8 |
| ; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP6]], align 8 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP8]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT5]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[INDEX]] to i64 |
| ; CHECK-NEXT: [[TMP16:%.*]] = shl i64 [[TMP9]], 5 |
| ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP16]] |
| ; CHECK-NEXT: [[TMP11:%.*]] = call <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64.p0.i64(ptr align 8 [[TMP10]], i64 32, <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-NEXT: [[TMP12:%.*]] = fsub <vscale x 2 x double> [[BROADCAST_SPLAT2]], [[TMP11]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = fmul <vscale x 2 x double> [[BROADCAST_SPLAT6]], [[TMP12]] |
| ; CHECK-NEXT: [[TMP14:%.*]] = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> [[TMP3]], <vscale x 2 x double> [[BROADCAST_SPLAT8]], <vscale x 2 x double> [[TMP13]]) |
| ; CHECK-NEXT: call void @llvm.vp.scatter.nxv2f64.nxv2p0(<vscale x 2 x double> [[TMP14]], <vscale x 2 x ptr> align 8 [[BROADCAST_SPLAT4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP7]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP7]] |
| ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @type_cache_crash( |
| ; CHECK-UF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i32 [[N:%.*]], double [[C0:%.*]], double [[C1:%.*]], double [[C2:%.*]], i64 [[C3:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 4) |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = add nsw i32 [[SMAX]], -1 |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1 |
| ; CHECK-UF2-NEXT: [[TMP3:%.*]] = call i32 @llvm.vscale.i32() |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = shl nuw i32 [[TMP3]], 2 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP2]], [[TMP4]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = shl nuw i32 [[TMP3]], 1 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], [[TMP4]] |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = icmp eq i32 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP4]], i32 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[TMP8]] |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x double> poison, double [[C0]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = shl i32 [[N_VEC]], 2 |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = fneg <vscale x 2 x double> [[BROADCAST_SPLAT]] |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = fsub double 0.000000e+00, [[C1]] |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP11]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT5]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[C3]] |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP12]], i64 48 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x double> poison, double [[C2]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: store double 0.000000e+00, ptr [[A]], align 8 |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = load double, ptr [[TMP13]], align 8 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <vscale x 2 x double> poison, double [[TMP14]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <vscale x 2 x double> [[BROADCAST_SPLATINSERT3]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = zext i32 [[INDEX]] to i64 |
| ; CHECK-UF2-NEXT: [[TMP29:%.*]] = shl i64 [[TMP15]], 5 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP29]] |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP5]] to i64 |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = mul i64 [[TMP17]], 32 |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP18]] |
| ; CHECK-UF2-NEXT: [[TMP20:%.*]] = call <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64.p0.i64(ptr align 8 [[TMP19]], i64 32, <vscale x 2 x i1> splat (i1 true), i32 [[TMP5]]) |
| ; CHECK-UF2-NEXT: [[TMP21:%.*]] = fsub <vscale x 2 x double> [[BROADCAST_SPLAT2]], [[TMP20]] |
| ; CHECK-UF2-NEXT: [[TMP22:%.*]] = fmul <vscale x 2 x double> [[BROADCAST_SPLAT4]], [[TMP21]] |
| ; CHECK-UF2-NEXT: [[TMP23:%.*]] = call <vscale x 2 x double> @llvm.fmuladd.nxv2f64(<vscale x 2 x double> [[TMP10]], <vscale x 2 x double> [[BROADCAST_SPLAT6]], <vscale x 2 x double> [[TMP22]]) |
| ; CHECK-UF2-NEXT: [[TMP24:%.*]] = call i32 @llvm.vscale.i32() |
| ; CHECK-UF2-NEXT: [[TMP25:%.*]] = mul nuw i32 [[TMP24]], 2 |
| ; CHECK-UF2-NEXT: [[TMP26:%.*]] = sub i32 [[TMP25]], 1 |
| ; CHECK-UF2-NEXT: [[TMP27:%.*]] = extractelement <vscale x 2 x double> [[TMP23]], i32 [[TMP26]] |
| ; CHECK-UF2-NEXT: store double [[TMP27]], ptr [[C]], align 8 |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP4]] |
| ; CHECK-UF2-NEXT: [[TMP28:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[NEG_C0:%.*]] = fneg double [[C0]] |
| ; CHECK-UF2-NEXT: [[IV_ADD:%.*]] = add i32 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[IV_SEXT:%.*]] = sext i32 [[IV_ADD]] to i64 |
| ; CHECK-UF2-NEXT: [[STRIDED_BASE:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[IV_SEXT]] |
| ; CHECK-UF2-NEXT: [[NEG_C1:%.*]] = fsub double 0.000000e+00, [[C1]] |
| ; CHECK-UF2-NEXT: store double 0.000000e+00, ptr [[A]], align 8 |
| ; CHECK-UF2-NEXT: [[UNIFORM_BASE:%.*]] = getelementptr [8 x i8], ptr [[B]], i64 [[C3]] |
| ; CHECK-UF2-NEXT: [[UNIFORM_PTR:%.*]] = getelementptr i8, ptr [[UNIFORM_BASE]], i64 48 |
| ; CHECK-UF2-NEXT: [[UNIFORM_VAL:%.*]] = load double, ptr [[UNIFORM_PTR]], align 8 |
| ; CHECK-UF2-NEXT: [[STRIDED_PTR:%.*]] = getelementptr i8, ptr [[STRIDED_BASE]], i64 -8 |
| ; CHECK-UF2-NEXT: [[STRIDED_VAL:%.*]] = load double, ptr [[STRIDED_PTR]], align 8 |
| ; CHECK-UF2-NEXT: [[DIFF:%.*]] = fsub double [[C2]], [[STRIDED_VAL]] |
| ; CHECK-UF2-NEXT: [[PROD:%.*]] = fmul double [[UNIFORM_VAL]], [[DIFF]] |
| ; CHECK-UF2-NEXT: [[RESULT:%.*]] = call double @llvm.fmuladd.f64(double [[NEG_C0]], double [[NEG_C1]], double [[PROD]]) |
| ; CHECK-UF2-NEXT: store double [[RESULT]], ptr [[C]], align 8 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nsw i32 [[IV]], 4 |
| ; CHECK-UF2-NEXT: [[CMP:%.*]] = icmp slt i32 [[IV_NEXT]], [[N]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i32 [ 0, %entry ], [ %iv_next, %loop ] |
| %neg_c0 = fneg double %c0 |
| %iv_add = add i32 %iv, 1 |
| %iv_sext = sext i32 %iv_add to i64 |
| %strided_base = getelementptr [8 x i8], ptr %b, i64 %iv_sext |
| %neg_c1 = fsub double 0.000000e+00, %c1 |
| store double 0.000000e+00, ptr %a, align 8 |
| %uniform_base = getelementptr [8 x i8], ptr %b, i64 %c3 |
| %uniform_ptr = getelementptr i8, ptr %uniform_base, i64 48 |
| %uniform_val = load double, ptr %uniform_ptr, align 8 |
| %strided_ptr = getelementptr i8, ptr %strided_base, i64 -8 |
| %strided_val = load double, ptr %strided_ptr, align 8 |
| %diff = fsub double %c2, %strided_val |
| %prod = fmul double %uniform_val, %diff |
| %result = call double @llvm.fmuladd.f64(double %neg_c0, double %neg_c1, double %prod) |
| store double %result, ptr %c, align 8 |
| %iv_next = add nsw i32 %iv, 4 |
| %cmp = icmp slt i32 %iv_next, %n |
| br i1 %cmp, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| define void @lshr_exact_stride(ptr noalias %in, ptr noalias %out) { |
| ; CHECK-LABEL: define void @lshr_exact_stride( |
| ; CHECK-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 512, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP5:%.*]] = shl nuw i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr nuw i8, ptr [[IN]], i64 [[TMP5]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP7]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr nuw i8, ptr [[OUT]], i64 [[TMP4]] |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[WIDE_MASKED_GATHER]], ptr align 4 [[TMP8]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP3]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP3]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @lshr_exact_stride( |
| ; CHECK-UF2-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP1]], i64 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 512, [[TMP5]] |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw i64 [[INDEX]], 2 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = add i64 [[TMP2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4 |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = add i64 [[TMP10]], [[TMP12]] |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = lshr exact i64 [[TMP10]], 1 |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = lshr exact i64 [[TMP13]], 1 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[TMP14]] |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[TMP15]] |
| ; CHECK-UF2-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i32>, ptr [[TMP16]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC]]) |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC1:%.*]] = load <vscale x 8 x i32>, ptr [[TMP17]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC2:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC1]]) |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP22:%.*]] = shl nuw i64 [[INDEX]], 4 |
| ; CHECK-UF2-NEXT: [[TMP23:%.*]] = getelementptr nuw i8, ptr [[OUT]], i64 [[TMP22]] |
| ; CHECK-UF2-NEXT: [[TMP24:%.*]] = mul i64 [[TMP2]], 16 |
| ; CHECK-UF2-NEXT: [[TMP21:%.*]] = getelementptr nuw i8, ptr [[TMP23]], i64 [[TMP24]] |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP18]], ptr align 4 [[TMP23]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP19]], ptr align 4 [[TMP21]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[SHR:%.*]] = lshr exact i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[SHR]] |
| ; CHECK-UF2-NEXT: [[L:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr nusw i32, ptr [[OUT]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: store i32 [[L]], ptr [[ARRAYIDX2]], align 4 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 4 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 2048 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %shr = lshr exact i64 %iv, 1 |
| %arrayidx = getelementptr nusw i32, ptr %in, i64 %shr |
| %l = load i32, ptr %arrayidx, align 4 |
| %arrayidx2 = getelementptr nusw i32, ptr %out, i64 %iv |
| store i32 %l, ptr %arrayidx2, align 4 |
| %iv.next = add nuw i64 %iv, 4 |
| %done = icmp eq i64 %iv.next, 2048 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define void @or_disjoint_stride(ptr noalias %in, ptr noalias %out) { |
| ; CHECK-LABEL: define void @or_disjoint_stride( |
| ; CHECK-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr nuw i8, ptr [[IN]], i64 4 |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr nuw i8, ptr [[TMP0]], i64 [[TMP2]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP3]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP1]]) |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr nusw i32, ptr [[OUT]], i64 [[INDEX]] |
| ; CHECK-NEXT: call void @llvm.vp.store.nxv4i32.p0(<vscale x 4 x i32> [[TMP4]], ptr align 4 [[TMP5]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP1]]) |
| ; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP1]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP6]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP6]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @or_disjoint_stride( |
| ; CHECK-UF2-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP1]], i64 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[TMP5]] |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = add i64 [[TMP2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 1 |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], [[TMP7]] |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[INDEX]], 1 |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw nsw i64 [[TMP8]], 1 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = or disjoint i64 [[TMP9]], 1 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = or disjoint i64 [[TMP10]], 1 |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[TMP11]] |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[TMP12]] |
| ; CHECK-UF2-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i32>, ptr [[TMP13]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC]]) |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC1:%.*]] = load <vscale x 8 x i32>, ptr [[TMP14]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC2:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC1]]) |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = getelementptr nusw i32, ptr [[OUT]], i64 [[INDEX]] |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = getelementptr nusw i32, ptr [[TMP17]], i64 [[TMP2]] |
| ; CHECK-UF2-NEXT: store <vscale x 4 x i32> [[TMP15]], ptr [[TMP17]], align 4 |
| ; CHECK-UF2-NEXT: store <vscale x 4 x i32> [[TMP16]], ptr [[TMP18]], align 4 |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[IDX:%.*]] = shl nuw nsw i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[OR:%.*]] = or disjoint i64 [[IDX]], 1 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[OR]] |
| ; CHECK-UF2-NEXT: [[L:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr nusw i32, ptr [[OUT]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: store i32 [[L]], ptr [[ARRAYIDX2]], align 4 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %idx = shl nuw nsw i64 %iv, 1 |
| %or = or disjoint i64 %idx, 1 |
| %arrayidx = getelementptr nusw i32, ptr %in, i64 %or |
| %l = load i32, ptr %arrayidx, align 4 |
| %arrayidx2 = getelementptr nusw i32, ptr %out, i64 %iv |
| store i32 %l, ptr %arrayidx2, align 4 |
| %iv.next = add nuw i64 %iv, 1 |
| %done = icmp eq i64 %iv.next, 1024 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define void @lshr_stride_no_exact(ptr noalias %in, ptr noalias %out) { |
| ; CHECK-LABEL: define void @lshr_stride_no_exact( |
| ; CHECK-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 512, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP5:%.*]] = shl i64 [[INDEX]], 3 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[IN]], i64 [[TMP5]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i64(ptr align 4 [[TMP7]], i64 8, <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[OUT]], i64 [[TMP4]] |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[WIDE_MASKED_GATHER]], ptr align 4 [[TMP8]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP3]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP3]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @lshr_stride_no_exact( |
| ; CHECK-UF2-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 [[TMP1]], i64 [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 512, [[TMP5]] |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = shl nuw i64 [[INDEX]], 2 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = add i64 [[TMP2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4 |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = add i64 [[TMP10]], [[TMP12]] |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = lshr i64 [[TMP10]], 1 |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 1 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[IN]], i64 [[TMP14]] |
| ; CHECK-UF2-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[IN]], i64 [[TMP15]] |
| ; CHECK-UF2-NEXT: [[WIDE_VEC:%.*]] = load <vscale x 8 x i32>, ptr [[TMP16]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC]]) |
| ; CHECK-UF2-NEXT: [[TMP18:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC]], 0 |
| ; CHECK-UF2-NEXT: [[WIDE_VEC1:%.*]] = load <vscale x 8 x i32>, ptr [[TMP17]], align 4 |
| ; CHECK-UF2-NEXT: [[STRIDED_VEC2:%.*]] = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> [[WIDE_VEC1]]) |
| ; CHECK-UF2-NEXT: [[TMP19:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[STRIDED_VEC2]], 0 |
| ; CHECK-UF2-NEXT: [[TMP22:%.*]] = shl i64 [[INDEX]], 4 |
| ; CHECK-UF2-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[OUT]], i64 [[TMP22]] |
| ; CHECK-UF2-NEXT: [[TMP24:%.*]] = mul i64 [[TMP2]], 16 |
| ; CHECK-UF2-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[TMP23]], i64 [[TMP24]] |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP18]], ptr align 4 [[TMP23]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[TMP19]], ptr align 4 [[TMP21]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP6]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[SHR:%.*]] = lshr i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX:%.*]] = getelementptr i32, ptr [[IN]], i64 [[SHR]] |
| ; CHECK-UF2-NEXT: [[L:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i32, ptr [[OUT]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: store i32 [[L]], ptr [[ARRAYIDX2]], align 4 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 4 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 2048 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %shr = lshr i64 %iv, 1 |
| %arrayidx = getelementptr i32, ptr %in, i64 %shr |
| %l = load i32, ptr %arrayidx, align 4 |
| %arrayidx2 = getelementptr i32, ptr %out, i64 %iv |
| store i32 %l, ptr %arrayidx2, align 4 |
| %iv.next = add nuw i64 %iv, 4 |
| %done = icmp eq i64 %iv.next, 2048 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define void @lshr_exact_stride_nonconstant(ptr noalias %in, ptr noalias %out, i64 %shift) { |
| ; CHECK-LABEL: define void @lshr_exact_stride_nonconstant( |
| ; CHECK-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]], i64 [[SHIFT:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[SHIFT]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; CHECK-NEXT: [[TMP1:%.*]] = mul nuw <vscale x 4 x i64> [[TMP0]], splat (i64 4) |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP1]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 512, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 4, i1 true) |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[TMP3]], 2 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP4]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP5:%.*]] = lshr exact <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] |
| ; CHECK-NEXT: [[WIDE_GEP:%.*]] = getelementptr nusw i32, ptr [[IN]], <vscale x 4 x i64> [[TMP5]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.vp.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[WIDE_GEP]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP8:%.*]] = shl nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr nuw i8, ptr [[OUT]], i64 [[TMP8]] |
| ; CHECK-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[WIDE_MASKED_GATHER]], ptr align 4 [[TMP7]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP3]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP3]] |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; CHECK-UF2-LABEL: define void @lshr_exact_stride_nonconstant( |
| ; CHECK-UF2-SAME: ptr noalias [[IN:%.*]], ptr noalias [[OUT:%.*]], i64 [[SHIFT:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP0]], 2 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP2]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 512, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 512, [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 2 |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = shl <vscale x 4 x i64> [[BROADCAST_SPLAT]], splat (i64 2) |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[SHIFT]], i64 0 |
| ; CHECK-UF2-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64() |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = mul nuw <vscale x 4 x i64> [[TMP6]], splat (i64 4) |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[VEC_IND:%.*]] = phi <vscale x 4 x i64> [ [[TMP7]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[STEP_ADD:%.*]] = add nuw <vscale x 4 x i64> [[VEC_IND]], [[TMP5]] |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = lshr exact <vscale x 4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT2]] |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = lshr exact <vscale x 4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT2]] |
| ; CHECK-UF2-NEXT: [[WIDE_GEP:%.*]] = getelementptr nusw i32, ptr [[IN]], <vscale x 4 x i64> [[TMP8]] |
| ; CHECK-UF2-NEXT: [[WIDE_GEP3:%.*]] = getelementptr nusw i32, ptr [[IN]], <vscale x 4 x i64> [[TMP9]] |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[WIDE_GEP]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison) |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER4:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 [[WIDE_GEP3]], <vscale x 4 x i1> splat (i1 true), <vscale x 4 x i32> poison) |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = shl nuw i64 [[INDEX]], 4 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = getelementptr nuw i8, ptr [[OUT]], i64 [[TMP11]] |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = mul i64 [[TMP2]], 16 |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr nuw i8, ptr [[TMP12]], i64 [[TMP13]] |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[WIDE_MASKED_GATHER]], ptr align 4 [[TMP12]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i64(<vscale x 4 x i32> [[WIDE_MASKED_GATHER4]], ptr align 4 [[TMP14]], i64 16, <vscale x 4 x i1> splat (i1 true), i32 [[TMP15]]) |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[VEC_IND_NEXT]] = add nuw <vscale x 4 x i64> [[STEP_ADD]], [[TMP5]] |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 512, [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[SHR:%.*]] = lshr exact i64 [[IV]], [[SHIFT]] |
| ; CHECK-UF2-NEXT: [[ARRAYIDX:%.*]] = getelementptr nusw i32, ptr [[IN]], i64 [[SHR]] |
| ; CHECK-UF2-NEXT: [[L:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 |
| ; CHECK-UF2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr nusw i32, ptr [[OUT]], i64 [[IV]] |
| ; CHECK-UF2-NEXT: store i32 [[L]], ptr [[ARRAYIDX2]], align 4 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 4 |
| ; CHECK-UF2-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 2048 |
| ; CHECK-UF2-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %shr = lshr exact i64 %iv, %shift |
| %arrayidx = getelementptr nusw i32, ptr %in, i64 %shr |
| %l = load i32, ptr %arrayidx, align 4 |
| %arrayidx2 = getelementptr nusw i32, ptr %out, i64 %iv |
| store i32 %l, ptr %arrayidx2, align 4 |
| %iv.next = add nuw i64 %iv, 4 |
| %done = icmp eq i64 %iv.next, 2048 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| ; The routine for creating strided accesses depends on SCEV expansion, |
| ; and we specifically test the case of IV-start being an AddRec. |
| define void @iv_start_is_addrec(ptr %p, ptr noalias %q) { |
| ; CHECK-LABEL: define void @iv_start_is_addrec( |
| ; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) #[[ATTR0]] { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: br label %[[PH:.*]] |
| ; CHECK: [[PH]]: |
| ; CHECK-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ] |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl i64 [[IND_INCOMING]], 2 |
| ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP0]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[Q]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 129, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 8, i1 true) |
| ; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[INDEX]], -8 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr align 1 [[TMP6]], i64 -8, <vscale x 8 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[WIDE_MASKED_GATHER]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP2]]) |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP3]], [[INDEX]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP3]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[IND_INCOMING_NEXT]] = add i64 [[IND_INCOMING]], 1 |
| ; CHECK-NEXT: br label %[[PH]] |
| ; |
| ; CHECK-UF2-LABEL: define void @iv_start_is_addrec( |
| ; CHECK-UF2-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]]) #[[ATTR0]] { |
| ; CHECK-UF2-NEXT: [[ENTRY:.*]]: |
| ; CHECK-UF2-NEXT: br label %[[PH:.*]] |
| ; CHECK-UF2: [[PH]]: |
| ; CHECK-UF2-NEXT: [[IND_INCOMING:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IND_INCOMING_NEXT:%.*]], %[[EXIT:.*]] ] |
| ; CHECK-UF2-NEXT: [[TMP6:%.*]] = shl i64 [[IND_INCOMING]], 2 |
| ; CHECK-UF2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP6]] |
| ; CHECK-UF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; CHECK-UF2-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 5 |
| ; CHECK-UF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 129, [[TMP1]] |
| ; CHECK-UF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| ; CHECK-UF2: [[VECTOR_PH]]: |
| ; CHECK-UF2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP0]], 4 |
| ; CHECK-UF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 129, [[TMP1]] |
| ; CHECK-UF2-NEXT: [[N_VEC:%.*]] = sub i64 129, [[N_MOD_VF]] |
| ; CHECK-UF2-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], -2 |
| ; CHECK-UF2-NEXT: [[TMP5:%.*]] = add i64 [[IND_INCOMING]], [[TMP4]] |
| ; CHECK-UF2-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-UF2-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK-UF2: [[VECTOR_BODY]]: |
| ; CHECK-UF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-UF2-NEXT: [[TMP8:%.*]] = mul i64 [[INDEX]], -8 |
| ; CHECK-UF2-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP8]] |
| ; CHECK-UF2-NEXT: [[TMP15:%.*]] = mul i64 [[TMP2]], -8 |
| ; CHECK-UF2-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[TMP14]], i64 [[TMP15]] |
| ; CHECK-UF2-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP16]], i64 -8, <vscale x 16 x i1> splat (i1 true), i32 [[TMP7]]) |
| ; CHECK-UF2-NEXT: [[TMP9:%.*]] = call i32 @llvm.vscale.i32() |
| ; CHECK-UF2-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP9]], 16 |
| ; CHECK-UF2-NEXT: [[TMP11:%.*]] = sub i32 [[TMP10]], 1 |
| ; CHECK-UF2-NEXT: [[TMP12:%.*]] = extractelement <vscale x 16 x i8> [[WIDE_MASKED_GATHER]], i32 [[TMP11]] |
| ; CHECK-UF2-NEXT: store i8 [[TMP12]], ptr [[Q]], align 1 |
| ; CHECK-UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] |
| ; CHECK-UF2-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[MIDDLE_BLOCK]]: |
| ; CHECK-UF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 129, [[N_VEC]] |
| ; CHECK-UF2-NEXT: br i1 [[CMP_N]], label %[[EXIT]], label %[[SCALAR_PH]] |
| ; CHECK-UF2: [[SCALAR_PH]]: |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[PH]] ] |
| ; CHECK-UF2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[IND_INCOMING]], %[[PH]] ] |
| ; CHECK-UF2-NEXT: br label %[[LOOP:.*]] |
| ; CHECK-UF2: [[LOOP]]: |
| ; CHECK-UF2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[IND:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IND_NEXT:%.*]], %[[LOOP]] ] |
| ; CHECK-UF2-NEXT: [[IND_NEXT]] = add i64 [[IND]], -2 |
| ; CHECK-UF2-NEXT: [[GEP_P_IND:%.*]] = getelementptr [4 x i8], ptr [[P]], i64 [[IND]] |
| ; CHECK-UF2-NEXT: [[LD_P:%.*]] = load i8, ptr [[GEP_P_IND]], align 1 |
| ; CHECK-UF2-NEXT: store i8 [[LD_P]], ptr [[Q]], align 1 |
| ; CHECK-UF2-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-UF2-NEXT: [[EC:%.*]] = icmp slt i64 [[IV]], 128 |
| ; CHECK-UF2-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], {{!llvm.loop ![0-9]+}} |
| ; CHECK-UF2: [[EXIT]]: |
| ; CHECK-UF2-NEXT: [[IND_INCOMING_NEXT]] = add i64 [[IND_INCOMING]], 1 |
| ; CHECK-UF2-NEXT: br label %[[PH]] |
| ; |
| entry: |
| br label %ph |
| |
| ph: |
| %ind.incoming = phi i64 [ 0, %entry ], [ %ind.incoming.next, %exit ] |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %ph ], [ %iv.next, %loop ] |
| %ind = phi i64 [ %ind.incoming, %ph ], [ %ind.next, %loop ] |
| %ind.next = add i64 %ind, -2 |
| %gep.p.ind = getelementptr [4 x i8], ptr %p, i64 %ind |
| %ld.p = load i8, ptr %gep.p.ind |
| store i8 %ld.p, ptr %q |
| %iv.next = add i64 %iv, 1 |
| %ec = icmp slt i64 %iv, 128 |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| %ind.incoming.next = add i64 %ind.incoming, 1 |
| br label %ph |
| } |
