blob: 1c6b88d5491594c54448e23a0cacb958c25654a5 [file]
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; REQUIRES: asserts
; RUN: opt -mtriple riscv64 -mattr=+v -p loop-vectorize -debug-only=loop-vectorize -S < %s 2>%t | FileCheck %s
; RUN: cat %t | FileCheck %s --check-prefix=COST
; COST: LV: Checking a loop in 'pointer_induction_stepvector_cost'
; COST: Cost of 0 for VF vscale x 1: EMIT vp<%6> = step-vector i32
; COST: Cost of 0 for VF vscale x 2: EMIT vp<%6> = step-vector i32
; COST: Cost of 0 for VF vscale x 4: EMIT vp<%6> = step-vector i32
; NOTE: All costs are invalid despite each individual operation having a valid cost.
; TODO: VPlan shows the step-vector instruction is not hoisted out of the loop.
define void @pointer_induction_stepvector_cost(ptr %src.start, ptr %dst.start, ptr %src.end) {
; CHECK-LABEL: define void @pointer_induction_stepvector_cost(
; CHECK-SAME: ptr [[SRC_START:%.*]], ptr [[DST_START:%.*]], ptr [[SRC_END:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
; CHECK-NEXT: [[DST:%.*]] = phi ptr [ [[DST_NEXT:%.*]], %[[LOOP]] ], [ [[DST_START]], %[[ENTRY]] ]
; CHECK-NEXT: [[SRC:%.*]] = phi ptr [ [[SRC_NEXT:%.*]], %[[LOOP]] ], [ [[SRC_START]], %[[ENTRY]] ]
; CHECK-NEXT: store i32 0, ptr [[DST]], align 2
; CHECK-NEXT: [[SRC_NEXT]] = getelementptr i8, ptr [[SRC]], i64 4
; CHECK-NEXT: [[DST_NEXT]] = getelementptr i8, ptr [[DST]], i64 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[SRC]], [[SRC_END]]
; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[LOOP]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%dst = phi ptr [ %dst.next, %loop ], [ %dst.start, %entry ]
%src = phi ptr [ %src.next, %loop ], [ %src.start, %entry ]
store i32 0, ptr %dst, align 2
%src.next = getelementptr i8, ptr %src, i64 4
%dst.next = getelementptr i8, ptr %dst, i64 4
%cmp = icmp eq ptr %src, %src.end
br i1 %cmp, label %exit, label %loop
exit:
ret void
}