llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.prefetch.data.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck --check-prefixes=GCN,GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck --check-prefixes=GFX1250-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu13.10 < %s | FileCheck --check-prefixes=GFX1310-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu13.10 < %s | FileCheck --check-prefixes=GFX1310-GISEL %s

define amdgpu_ps void @prefetch_data_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
; GCN-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_sgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_imm_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
; GCN-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x200, s2, 0
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x200, s2, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x200, s2, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x200, s2, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x200, s2, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_base_imm_len(ptr addrspace(4) inreg %ptr) {
; GCN-LABEL: prefetch_data_sgpr_base_imm_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 31)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_imm_base_imm_len(ptr addrspace(4) inreg %ptr) {
; GCN-LABEL: prefetch_data_sgpr_imm_base_imm_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x200, null, 31
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_imm_base_imm_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x200, null, 31
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_imm_base_imm_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x200, null, 31
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_imm_base_imm_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x200, null, 31
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_imm_base_imm_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x200, null, 31
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 31)
  ret void
}

define amdgpu_ps void @prefetch_data_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
; GCN-LABEL: prefetch_data_vgpr_base_sgpr_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    v_readfirstlane_b32 s3, v1
; GCN-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_vgpr_base_sgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_vgpr_base_sgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_vgpr_base_sgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1310-SDAG-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_vgpr_base_sgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1310-GISEL-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
  ret void
}

define amdgpu_ps void @prefetch_data_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
; SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; SDAG:       ; %bb.0: ; %entry
; SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; SDAG-NEXT:    s_prefetch_data s[2:3], 0x200, s0, 0
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; GISEL:       ; %bb.0: ; %entry
; GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x200, v0
; GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GISEL-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GISEL-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-SDAG-NEXT:    s_prefetch_data s[2:3], 0x200, s0, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x200, v0
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1250-GISEL-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1310-SDAG-NEXT:    s_prefetch_data s[2:3], 0x200, s0, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    v_add_co_u32 v0, vcc_lo, 0x200, v0
; GFX1310-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1310-GISEL-NEXT:    v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s3, v1
; GFX1310-GISEL-NEXT:    s_prefetch_data s[2:3], 0x0, s0, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_base_vgpr_len(ptr addrspace(4) inreg %ptr, i32 %len) {
; GCN-LABEL: prefetch_data_sgpr_base_vgpr_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_readfirstlane_b32 s2, v0
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_vgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_vgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_vgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_vgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_global(ptr addrspace(1) inreg %ptr) {
; GCN-LABEL: prefetch_data_sgpr_base_imm_len_global:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_global:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_global:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_global:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_global:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 31)
  ret void
}

define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_flat(ptr inreg %ptr) {
; GCN-LABEL: prefetch_data_sgpr_base_imm_len_flat:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_flat:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_flat:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_sgpr_base_imm_len_flat:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_sgpr_base_imm_len_flat:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 31
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 31)
  ret void
}

define amdgpu_ps void @prefetch_data_vgpr_base_imm_len(ptr addrspace(4) %ptr) {
; GCN-LABEL: prefetch_data_vgpr_base_imm_len:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_readfirstlane_b32 s0, v0
; GCN-NEXT:    v_readfirstlane_b32 s1, v1
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GCN-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_vgpr_base_imm_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_vgpr_base_imm_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_vgpr_base_imm_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_vgpr_base_imm_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 0)
  ret void
}

define amdgpu_ps void @prefetch_data_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) {
; SDAG-LABEL: prefetch_data_vgpr_base_vgpr_len:
; SDAG:       ; %bb.0: ; %entry
; SDAG-NEXT:    v_readfirstlane_b32 s2, v2
; SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; SDAG-NEXT:    v_readfirstlane_b32 s1, v1
; SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: prefetch_data_vgpr_base_vgpr_len:
; GISEL:       ; %bb.0: ; %entry
; GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; GISEL-NEXT:    v_readfirstlane_b32 s1, v1
; GISEL-NEXT:    v_readfirstlane_b32 s2, v2
; GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GISEL-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: prefetch_data_vgpr_base_vgpr_len:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s2, v2
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1250-SDAG-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: prefetch_data_vgpr_base_vgpr_len:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1250-GISEL-NEXT:    v_readfirstlane_b32 s2, v2
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1250-GISEL-NEXT:    s_endpgm
;
; GFX1310-SDAG-LABEL: prefetch_data_vgpr_base_vgpr_len:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s2, v2
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1310-SDAG-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-SDAG-NEXT:    s_endpgm
;
; GFX1310-GISEL-LABEL: prefetch_data_vgpr_base_vgpr_len:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s1, v1
; GFX1310-GISEL-NEXT:    v_readfirstlane_b32 s2, v2
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, s2, 0
; GFX1310-GISEL-NEXT:    s_endpgm
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
  ret void
}

define amdgpu_ps float @prefetch_and_load_b32(ptr addrspace(4) align 4 inreg %p) {
; GCN-LABEL: prefetch_and_load_b32:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GCN-NEXT:    s_load_b32 s0, s[0:1], 0x0
; GCN-NEXT:    s_wait_kmcnt 0x0
; GCN-NEXT:    v_mov_b32_e32 v0, s0
; GCN-NEXT:    ; return to shader part epilog
;
; GFX1250-SDAG-LABEL: prefetch_and_load_b32:
; GFX1250-SDAG:       ; %bb.0: ; %entry
; GFX1250-SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-SDAG-NEXT:    v_nop
; GFX1250-SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-SDAG-NEXT:    s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX1250-SDAG-NEXT:    ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: prefetch_and_load_b32:
; GFX1250-GISEL:       ; %bb.0: ; %entry
; GFX1250-GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT:    v_nop
; GFX1250-GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX1250-GISEL-NEXT:    ; return to shader part epilog
;
; GFX1310-SDAG-LABEL: prefetch_and_load_b32:
; GFX1310-SDAG:       ; %bb.0: ; %entry
; GFX1310-SDAG-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1310-SDAG-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1310-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1310-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX1310-SDAG-NEXT:    ; return to shader part epilog
;
; GFX1310-GISEL-LABEL: prefetch_and_load_b32:
; GFX1310-GISEL:       ; %bb.0: ; %entry
; GFX1310-GISEL-NEXT:    s_prefetch_data s[0:1], 0x0, null, 0
; GFX1310-GISEL-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1310-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1310-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX1310-GISEL-NEXT:    ; return to shader part epilog
entry:
  tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %p, i32 0)
  %ret = load float, ptr addrspace(4) %p, align 4
  ret float %ret
}

declare void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
declare void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 %len)
declare void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 %len)