| commit | f1978d19a4ab28d0684d036973a50f65f1e08fae | [log] [tgz] |
|---|---|---|
| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | Wed Feb 14 06:23:14 2024 -0800 |
| committer | Tom Stellard <tstellar@redhat.com> | Mon Feb 26 17:38:41 2024 -0800 |
| tree | 62bbfb41fb4e16933557a678be14018bd4dbd85a | |
| parent | 83283342c38e03fc501c84b9fad7cd62f1d629d3 [diff] |
[AArch64] Initial Ampere1B scheduling model (#81341) The Ampere1B core is enabled with a new scheduling/pipeline model, as it provides significant updates over the Ampere1 core; it reduces latencies on many instructions, has some micro-ops reassigned between the XY and X units, and provides modelling for the instructions added since Ampere1 and Ampere1A. As this is the first model implementing the CSSC instructions, we update the UnsupportedFeatures on all other models (that have CompleteModel set). Testcases are added under llvm-mca: these showed the FullFP16 feature missing, so we are adding it in as part of this commit. This *adds tests and additional fixes* compared to the reverted #81338. (cherry picked from commit dd1897c6cb028bda7d4d541d1bb33965eccf0a68)
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