)]}'
{
  "commit": "f1978d19a4ab28d0684d036973a50f65f1e08fae",
  "tree": "62bbfb41fb4e16933557a678be14018bd4dbd85a",
  "parents": [
    "83283342c38e03fc501c84b9fad7cd62f1d629d3"
  ],
  "author": {
    "name": "Philipp Tomsich",
    "email": "philipp.tomsich@vrull.eu",
    "time": "Wed Feb 14 06:23:14 2024 -0800"
  },
  "committer": {
    "name": "Tom Stellard",
    "email": "tstellar@redhat.com",
    "time": "Mon Feb 26 17:38:41 2024 -0800"
  },
  "message": "[AArch64] Initial Ampere1B scheduling model (#81341)\n\nThe Ampere1B core is enabled with a new scheduling/pipeline model, as it\nprovides significant updates over the Ampere1 core; it reduces latencies\non many instructions, has some micro-ops reassigned between the XY and X\nunits, and provides modelling for the instructions added since Ampere1\nand Ampere1A.\n\nAs this is the first model implementing the CSSC instructions, we update\nthe UnsupportedFeatures on all other models (that have CompleteModel\nset).\n\nTestcases are added under llvm-mca: these showed the FullFP16 feature\nmissing, so we are adding it in as part of this commit.\n\nThis *adds tests and additional fixes* compared to the reverted #81338.\n\n(cherry picked from commit dd1897c6cb028bda7d4d541d1bb33965eccf0a68)\n",
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