| # RUN: llvm-mc -triple=arc -disassemble %s | FileCheck %s |
| |
| # CHECK: ld %r0, [%r0,0] |
| 0x00 0x10 0x00 0x00 |
| |
| # CHECK: ldh %r0, [%r0,0] |
| 0x00 0x10 0x00 0x01 |
| |
| # CHECK: ldb %r0, [%r0,0] |
| 0x00 0x10 0x80 0x00 |
| |
| # CHECK: ld %r1, [%r0,12] |
| 0x0c 0x10 0x01 0x00 |
| |
| # CHECK: ld %r14, [%fp,-12] |
| 0xf4 0x13 0x0e 0xb0 |
| |
| # CHECK: ld %r3, [%r0,-12] |
| 0xf4 0x10 0x03 0x80 |
| |
| # CHECK: ld %r0, [%r0,244] |
| 0xf4 0x10 0x00 0x00 |
| |
| # CHECK: ld %r0, [%r0,-12] |
| 0xf4 0x10 0x00 0x80 |
| |
| # CHECK: ldh.x %r3, [%r1,0] |
| 0x00 0x11 0x43 0x01 |
| |
| # CHECK: ldh.x %r2, [%r1,2] |
| 0x02 0x11 0x42 0x01 |
| |
| # CHECK: ldh.x %r2, [%fp,-132] |
| 0x7c 0x13 0x42 0xb1 |
| |
| # CHECK: ld %r0, [%r0,64000] |
| 0x30 0x20 0x80 0x0f 0x00 0x00 0x00 0xfa |
| |
| # CHECK: ld %r6, [63920] |
| 0x00 0x16 0x06 0x70 0x00 0x00 0xb0 0xf9 |
| |
| # CHECK: stb %r2, [%sp,35] |
| 0x23 0x1c 0x82 0x30 |
| |
| # CHECK: st %r7, [63920] |
| 0x00 0x1e 0xc0 0x71 0x00 0x00 0xb0 0xf9 |
| |
| # CHECK: ldb.ab %r1, [%r0,1] |
| 0x01 0x10 0x81 0x04 |
| |
| # CHECK: stb.ab %r2, [%r0,1] |
| 0x01 0x18 0x92 0x00 |
| |
| # CHECK: ldh.ab %r3, [%r0,12] |
| 0x0C 0x10 0x03 0x05 |
| |
| # CHECK: sth.ab %r4, [%r0,18] |
| 0x12 0x18 0x14 0x01 |
| |
| # CHECK: ld.ab %r5, [%r2,128] |
| 0x80 0x12 0x05 0x04 |
| |
| # CHECK: st.ab %r6, [%r2,64] |
| 0x40 0x1A 0x90 0x01 |
| |
| # CHECK: ldb.aw %r7, [%r0,1] |
| 0x01 0x10 0x87 0x02 |
| |
| # CHECK: stb.aw %r8, [%r0,1] |
| 0x01 0x18 0x0A 0x02 |
| |
| # CHECK: ldh.aw %r3, [%r0,12] |
| 0x0C 0x10 0x03 0x03 |
| |
| # CHECK: sth.aw %r3, [%r0,18] |
| 0x12 0x18 0xCC 0x00 |
| |
| # CHECK: ld.aw %r6, [%r2,128] |
| 0x80 0x12 0x06 0x02 |
| |
| # CHECK: st.aw %r6, [%r2,64] |
| 0x40 0x1A 0x88 0x01 |
| |
| # CHECK: ld.aw %r6, [%r2,128] |
| 0x80 0x12 0x06 0x02 |
| |
| # CHECK: st.aw %r6, [%r2,64] |
| 0x40 0x1A 0x88 0x01 |
| |
| # CHECK: ldb.x.di.aw %r0, [%r8,8] |
| 0x08 0x10 0xC0 0x1A |
| |
| # CHECK: stb.di.ab %r0, [%r9,64] |
| 0x40 0x19 0x32 0x10 |
| |
| # LR instructions with a U6 immediate bit pattern |
| # ([33] maps to the [%count0] auxilary register) |
| |
| # CHECK: lr %r0, [33] |
| 0x6a 0x20 0x40 0x08 |
| |
| # CHECK: lr %r7, [33] |
| 0x6a 0x27 0x40 0x08 |
| |
| # CHECK: lr %r15, [33] |
| 0x6a 0x27 0x40 0x18 |
| |
| # CHECK: lr %r22, [33] |
| 0x6a 0x26 0x40 0x28 |
| |
| # LR instructions with an S12 immediate bit pattern |
| |
| # CHECK: lr %r0, [33] |
| 0xaa 0x20 0x40 0x08 |
| |
| # The following don't necessarily map to real auxilary registers, but |
| # the different range of numbers helps exercise the S12 decoder. |
| |
| # CHECK: lr %r0, [-33] |
| 0xaa 0x20 0x60 0x08 |
| |
| # CHECK: lr %r0, [97] |
| 0xaa 0x20 0x41 0x08 |
| |
| # CHECK: lr %r0, [-97] |
| 0xaa 0x20 0x61 0x08 |
