llvm/test/CodeGen/AMDGPU/scalarize-insert-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GCN %s

define void @scalarize_insert_subvector(ptr addrspace(3) %inptr, ptr addrspace(3) %inptr1, ptr addrspace(3) %outptr) {
; GCN-LABEL: scalarize_insert_subvector:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    ds_read_b64 v[4:5], v0
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    ds_read_b32 v5, v1 offset:4
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    ds_write_b64 v2, v[4:5]
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %load0 = load <2 x i32>, ptr addrspace(3) %inptr, align 8
  %load1= load <2 x i32>, ptr addrspace(3) %inptr1, align 8
  %shuffle0 = shufflevector <2 x i32> %load1, <2 x i32> poison, <1 x i32> <i32 1>
  %bitcast0 = bitcast <1 x i32> %shuffle0 to <2 x half>
  %bitcast1 = bitcast <2 x i32> %load0 to <4 x half>
  %shuffle1 = shufflevector <2 x half> %bitcast0, <2 x half> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
  %shuffle2 = shufflevector <4 x half> %bitcast1, <4 x half> %shuffle1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
  store <4 x half> %shuffle2, ptr addrspace(3) %outptr
  ret void
}