llvm/test/CodeGen/AArch64/vector-div-by-promoted-const-no-assertion.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s | FileCheck %s

target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64-pc-windows-msvc"

define <16 x i16> @udiv_v16i16_from_zext(<16 x i8> %x) {
; CHECK-LABEL: udiv_v16i16_from_zext:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov w8, #21846 // =0x5556
; CHECK-NEXT:    ushll2 v1.8h, v0.16b, #0
; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
; CHECK-NEXT:    dup v2.8h, w8
; CHECK-NEXT:    umull2 v3.4s, v1.8h, v2.8h
; CHECK-NEXT:    umull v1.4s, v1.4h, v2.4h
; CHECK-NEXT:    umull2 v4.4s, v0.8h, v2.8h
; CHECK-NEXT:    umull v0.4s, v0.4h, v2.4h
; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v3.8h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v4.8h
; CHECK-NEXT:    ret
entry:
  %zext = zext <16 x i8> %x to <16 x i16>
  %div = udiv <16 x i16> %zext, splat (i16 3)
  ret <16 x i16> %div
}

define <16 x i16> @sdiv_v16i16_from_sext(<16 x i8> %x) {
; CHECK-LABEL: sdiv_v16i16_from_sext:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov w8, #21846 // =0x5556
; CHECK-NEXT:    sshll2 v1.8h, v0.16b, #0
; CHECK-NEXT:    sshll v0.8h, v0.8b, #0
; CHECK-NEXT:    dup v2.8h, w8
; CHECK-NEXT:    smull2 v3.4s, v1.8h, v2.8h
; CHECK-NEXT:    smull v1.4s, v1.4h, v2.4h
; CHECK-NEXT:    smull2 v4.4s, v0.8h, v2.8h
; CHECK-NEXT:    smull v0.4s, v0.4h, v2.4h
; CHECK-NEXT:    uzp2 v1.8h, v1.8h, v3.8h
; CHECK-NEXT:    uzp2 v0.8h, v0.8h, v4.8h
; CHECK-NEXT:    usra v1.8h, v1.8h, #15
; CHECK-NEXT:    usra v0.8h, v0.8h, #15
; CHECK-NEXT:    ret
entry:
  %sext = sext <16 x i8> %x to <16 x i16>
  %div = sdiv <16 x i16> %sext, splat (i16 3)
  ret <16 x i16> %div
}

define <16 x i16> @udiv_exact_v16i16_from_zext(<16 x i8> %x) {
; CHECK-LABEL: udiv_exact_v16i16_from_zext:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov w8, #43691 // =0xaaab
; CHECK-NEXT:    ushll v2.8h, v0.8b, #0
; CHECK-NEXT:    ushll2 v0.8h, v0.16b, #0
; CHECK-NEXT:    dup v3.8h, w8
; CHECK-NEXT:    mul v1.8h, v0.8h, v3.8h
; CHECK-NEXT:    mul v0.8h, v2.8h, v3.8h
; CHECK-NEXT:    ret
entry:
  %zext = zext <16 x i8> %x to <16 x i16>
  %div = udiv exact <16 x i16> %zext, splat (i16 3)
  ret <16 x i16> %div
}

define <16 x i16> @sdiv_exact_v16i16_from_sext(<16 x i8> %x) {
; CHECK-LABEL: sdiv_exact_v16i16_from_sext:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    mov w8, #43691 // =0xaaab
; CHECK-NEXT:    sshll v2.8h, v0.8b, #0
; CHECK-NEXT:    sshll2 v0.8h, v0.16b, #0
; CHECK-NEXT:    dup v3.8h, w8
; CHECK-NEXT:    mul v1.8h, v0.8h, v3.8h
; CHECK-NEXT:    mul v0.8h, v2.8h, v3.8h
; CHECK-NEXT:    ret
entry:
  %sext = sext <16 x i8> %x to <16 x i16>
  %div = sdiv exact <16 x i16> %sext, splat (i16 3)
  ret <16 x i16> %div
}