llvm/test/CodeGen/AArch64/sve-zext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 -mattr=+sve --aarch64-sve-vector-bits-min=256 < %s | FileCheck %s

define <vscale x 16 x i8> @zext_slt_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: zext_slt_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    cmpgt p1.b, p0/z, z1.b, z0.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 16 x i8> %a, %b
  %zext = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %zext
}

define <vscale x 16 x i8> @zext_slt_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: zext_slt_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.b, p0, z0.b, z1.b
; CHECK-NEXT:    splice z2.b, p0, z2.b, z3.b
; CHECK-NEXT:    ptrue p0.b, vl32
; CHECK-NEXT:    cmpgt p1.b, p0/z, z2.b, z0.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp slt <32 x i8> %a, %b
  %zext = zext <32 x i1> %cmp to <32 x i8>
  %insert = tail call <vscale x 16 x i8> @llvm.vector.insert(<vscale x 16 x i8> poison, <32 x i8> %zext, i64 0)
  ret <vscale x 16 x i8> %insert
}

define <vscale x 16 x i8> @zext_ult_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: zext_ult_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    cmphi p1.b, p0/z, z1.b, z0.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp ult <vscale x 16 x i8> %a, %b
  %zext = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %zext
}

define <vscale x 16 x i8> @zext_ult_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: zext_ult_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.b, p0, z0.b, z1.b
; CHECK-NEXT:    splice z2.b, p0, z2.b, z3.b
; CHECK-NEXT:    ptrue p0.b, vl32
; CHECK-NEXT:    cmphi p1.b, p0/z, z2.b, z0.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp ult <32 x i8> %a, %b
  %zext = zext <32 x i1> %cmp to <32 x i8>
  %insert = tail call <vscale x 16 x i8> @llvm.vector.insert(<vscale x 16 x i8> poison, <32 x i8> %zext, i64 0)
  ret <vscale x 16 x i8> %insert
}

define <vscale x 16 x i8> @zext_sgt_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: zext_sgt_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    cmpgt p1.b, p0/z, z0.b, z1.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp sgt <vscale x 16 x i8> %a, %b
  %zext = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %zext
}

define <vscale x 16 x i8> @zext_sgt_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: zext_sgt_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z2.b, p0, z2.b, z3.b
; CHECK-NEXT:    splice z0.b, p0, z0.b, z1.b
; CHECK-NEXT:    ptrue p0.b, vl32
; CHECK-NEXT:    cmpgt p1.b, p0/z, z0.b, z2.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp sgt <32 x i8> %a, %b
  %zext = zext <32 x i1> %cmp to <32 x i8>
  %insert = tail call <vscale x 16 x i8> @llvm.vector.insert(<vscale x 16 x i8> poison, <32 x i8> %zext, i64 0)
  ret <vscale x 16 x i8> %insert
}

define <vscale x 16 x i8> @zext_ugt_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: zext_ugt_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    cmphi p1.b, p0/z, z0.b, z1.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp ugt <vscale x 16 x i8> %a, %b
  %zext = zext <vscale x 16 x i1> %cmp to <vscale x 16 x i8>
  ret <vscale x 16 x i8> %zext
}

define <vscale x 16 x i8> @zext_ugt_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: zext_ugt_v32i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.b, vl16
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z2.b, p0, z2.b, z3.b
; CHECK-NEXT:    splice z0.b, p0, z0.b, z1.b
; CHECK-NEXT:    ptrue p0.b, vl32
; CHECK-NEXT:    cmphi p1.b, p0/z, z0.b, z2.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp ugt <32 x i8> %a, %b
  %zext = zext <32 x i1> %cmp to <32 x i8>
  %insert = tail call <vscale x 16 x i8> @llvm.vector.insert(<vscale x 16 x i8> poison, <32 x i8> %zext, i64 0)
  ret <vscale x 16 x i8> %insert
}

define <vscale x 2 x i64> @zext_slt_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: zext_slt_nxv2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    cmpgt p1.d, p0/z, z1.d, z0.d
; CHECK-NEXT:    mov z0.d, p1/z, #1 // =0x1
; CHECK-NEXT:    ret
  %cmp = icmp slt <vscale x 2 x i64> %a, %b
  %zext = zext <vscale x 2 x i1> %cmp to <vscale x 2 x i64>
  ret <vscale x 2 x i64> %zext
}

define <vscale x 2 x i64> @zext_slt_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: zext_slt_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    cmgt v0.2d, v1.2d, v0.2d
; CHECK-NEXT:    and z0.d, z0.d, #0x1
; CHECK-NEXT:    ret
  %cmp = icmp slt <2 x i64> %a, %b
  %zext = zext <2 x i1> %cmp to <2 x i64>
  %insert = tail call <vscale x 2 x i64> @llvm.vector.insert(<vscale x 2 x i64> poison, <2 x i64> %zext, i64 0)
  ret <vscale x 2 x i64> %insert
}

define <8 x i32> @zext_slt_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: zext_slt_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
; CHECK-NEXT:    splice z2.s, p0, z2.s, z3.s
; CHECK-NEXT:    ptrue p0.s, vl8
; CHECK-NEXT:    cmpgt p1.s, p0/z, z2.s, z0.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %cmp = icmp slt <8 x i32> %a, %b
  %zext = zext <8 x i1> %cmp to <8 x i32>
  ret <8 x i32> %zext
}

define <8 x i32> @zext_sle_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: zext_sle_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
; CHECK-NEXT:    splice z2.s, p0, z2.s, z3.s
; CHECK-NEXT:    ptrue p0.s, vl8
; CHECK-NEXT:    cmpge p1.s, p0/z, z2.s, z0.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %cmp = icmp sle <8 x i32> %a, %b
  %zext = zext <8 x i1> %cmp to <8 x i32>
  ret <8 x i32> %zext
}

define <8 x i32> @zext_sge_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: zext_sge_v8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.s, vl4
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z2.s, p0, z2.s, z3.s
; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
; CHECK-NEXT:    ptrue p0.s, vl8
; CHECK-NEXT:    cmpge p1.s, p0/z, z0.s, z2.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %cmp = icmp sge <8 x i32> %a, %b
  %zext = zext <8 x i1> %cmp to <8 x i32>
  ret <8 x i32> %zext
}

define <vscale x 16 x i8> @zext_nxv16i8(<vscale x 16 x i1> %p) {
; CHECK-LABEL: zext_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.b, p0/z, #1 // =0x1
; CHECK-NEXT:    ret
  %sext = sext <vscale x 16 x i1> %p to <vscale x 16 x i8>
  %and = and <vscale x 16 x i8> %sext, splat (i8 1)
  ret <vscale x 16 x i8> %and
}

define <vscale x 16 x i8> @splat_not_one_no_zext_nxv16i8(<vscale x 16 x i1> %p) {
; CHECK-LABEL: splat_not_one_no_zext_nxv16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    and z0.b, z0.b, #0x2
; CHECK-NEXT:    ret
  %sext = sext <vscale x 16 x i1> %p to <vscale x 16 x i8>
  %and = and <vscale x 16 x i8> %sext, splat (i8 2)
  ret <vscale x 16 x i8> %and
}

define <vscale x 4 x i32> @no_sext_i1_no_zext_nxv4i32(<vscale x 4 x i8> %p) {
; CHECK-LABEL: no_sext_i1_no_zext_nxv4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    and z0.s, z0.s, #0x1
; CHECK-NEXT:    ret
  %sext = sext <vscale x 4 x i8> %p to <vscale x 4 x i32>
  %and = and <vscale x 4 x i32> %sext, splat (i32 1)
  ret <vscale x 4 x i32> %and
}