llvm/test/CodeGen/AArch64/regalloc-hint-movprfx-streaming.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64 -mattr=+sme2 -force-streaming -start-before=greedy -stop-after=virtregrewriter %s -o - | FileCheck %s

# Check the register allocator gets hints to reuse registers of one of its operands.
---
name:            prioritize_movprfx_hints
tracksRegLiveness: true
isSSA:           false
noVRegs:         false
body:             |
  bb.0.entry:
    liveins: $z0, $z1, $z2, $z3, $p0

    ; CHECK-LABEL: name: prioritize_movprfx_hints
    ; CHECK: liveins: $p0, $z0, $z1, $z2, $z3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $z0 = SDIV_ZPZZ_D_UNDEF $p0, killed renamable $z0, killed renamable $z1
    ; CHECK-NEXT: renamable $z2 = MUL_ZPZZ_D_UNDEF $p0, killed renamable $z2, killed renamable $z3
    ; CHECK-NEXT: renamable $z0 = MUL_ZPZZ_D_UNDEF $p0, killed renamable $z2, killed renamable $z0
    ; CHECK-NEXT: RET_ReallyLR implicit $z0
    %0:zpr = COPY $z3
    %1:zpr = COPY $z2
    %2:zpr = COPY $z1
    %3:zpr = COPY $z0
    %4:zpr = SDIV_ZPZZ_D_UNDEF $p0, %3:zpr, %2:zpr
    %5:zpr = MUL_ZPZZ_D_UNDEF $p0, %1:zpr, %0:zpr
    %6:zpr = MUL_ZPZZ_D_UNDEF $p0, %5:zpr, %4:zpr
    $z0 = COPY %6:zpr
    RET_ReallyLR implicit $z0
...

# Check the register allocator prioritises hints that are set by the register
# allocator itself (i.e. to use z4 for the result register).
---
name:            prioritize_regalloc_hints
isSSA:           false
noVRegs:         false
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: prioritize_regalloc_hints
    ; CHECK: renamable $z0 = FDUP_ZI_S 0, implicit $vg
    ; CHECK-NEXT: renamable $z1 = FDUP_ZI_S 16, implicit $vg
    ; CHECK-NEXT: renamable $z2 = FDUP_ZI_S 32, implicit $vg
    ; CHECK-NEXT: renamable $p0 = PTRUE_S 31, implicit $vg
    ; CHECK-NEXT: renamable $z4 = FMLA_ZPZZZ_S_UNDEF killed renamable $p0, killed renamable $z0, killed renamable $z1, killed renamable $z2
    ; CHECK-NEXT: RET_ReallyLR implicit $z4
    %0:zpr = FDUP_ZI_S 0, implicit $vg
    %1:zpr = FDUP_ZI_S 16, implicit $vg
    %2:zpr = FDUP_ZI_S 32, implicit $vg
    %3:ppr_3b = PTRUE_S 31, implicit $vg
    %4:zpr = FMLA_ZPZZZ_S_UNDEF %3, %0, %1, %2
    $z4 = COPY %4
    RET_ReallyLR implicit $z4
...

# Check the register allocator gets hints to reuse registers of one of its
# operands, which are a subreg of a multi-register RegisterClass.
---
name:            prioritize_subreg_hints
tracksRegLiveness: true
isSSA:           false
noVRegs:         false
body:             |
  bb.0.entry:
    liveins: $x0, $x1, $x2

    ; CHECK-LABEL: name: prioritize_subreg_hints
    ; CHECK: liveins: $x0, $x1, $x2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $pn8 = PTRUE_C_B implicit $vg
    ; CHECK-NEXT: renamable $z16_z24 = LD1B_2Z_IMM_PSEUDO killed renamable $pn8, killed renamable $x2, 0
    ; CHECK-NEXT: renamable $z16 = ADD_ZI_B_PSEUDO renamable $z16, 5, 0
    ; CHECK-NEXT: renamable $z24 = ADD_ZI_B_PSEUDO killed renamable $z24, 5, 0
    ; CHECK-NEXT: STR_ZXI killed renamable $z16, killed renamable $x0, 0
    ; CHECK-NEXT: STR_ZXI killed renamable $z24, killed renamable $x1, 0
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:gpr64common = COPY $x1
    %2:gpr64common = COPY $x2
    %3:pnr_p8to15 = PTRUE_C_B implicit $vg
    %4:zpr2stridedorcontiguous = LD1B_2Z_IMM_PSEUDO %3, %2, 0
    %7:zpr = ADD_ZI_B_PSEUDO %4.zsub0, 5, 0
    %8:zpr = ADD_ZI_B_PSEUDO %4.zsub1, 5, 0
    STR_ZXI %7, %0, 0
    STR_ZXI %8, %1, 0
    RET_ReallyLR
...