llvm/test/CodeGen/AArch64/arm64-vcvtxd_f32_f64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK

define float @fcvtxn(double %a) {
; CHECK-LABEL: fcvtxn:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtxn s0, d0
; CHECK-NEXT:    ret
  %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
  ret float %vcvtxd.i
}