llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck -enable-var-scope %s

;; Test various conversions.
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
; CHECK-LABEL: trunc_:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    strb w0, [sp, #15]
; CHECK-NEXT:    strh w1, [sp, #12]
; CHECK-NEXT:    str w2, [sp, #8]
; CHECK-NEXT:    str x3, [sp]
; CHECK-NEXT:    ldr x8, [sp]
; CHECK-NEXT:    ; kill: def $w8 killed $w8 killed $x8
; CHECK-NEXT:    str w8, [sp, #8]
; CHECK-NEXT:    ldr w8, [sp, #8]
; CHECK-NEXT:    strh w8, [sp, #12]
; CHECK-NEXT:    ldrh w8, [sp, #12]
; CHECK-NEXT:    strb w8, [sp, #15]
; CHECK-NEXT:    ldrb w0, [sp, #15]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
entry:
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, ptr %a.addr, align 1
  store i16 %b, ptr %b.addr, align 2
  store i32 %c, ptr %c.addr, align 4
  store i64 %d, ptr %d.addr, align 8
  %tmp = load i64, ptr %d.addr, align 8
  %conv = trunc i64 %tmp to i32
  store i32 %conv, ptr %c.addr, align 4
  %tmp1 = load i32, ptr %c.addr, align 4
  %conv2 = trunc i32 %tmp1 to i16
  store i16 %conv2, ptr %b.addr, align 2
  %tmp3 = load i16, ptr %b.addr, align 2
  %conv4 = trunc i16 %tmp3 to i8
  store i8 %conv4, ptr %a.addr, align 1
  %tmp5 = load i8, ptr %a.addr, align 1
  %conv6 = zext i8 %tmp5 to i32
  ret i32 %conv6
}

define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
; CHECK-LABEL: zext_:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    strb w0, [sp, #15]
; CHECK-NEXT:    strh w1, [sp, #12]
; CHECK-NEXT:    str w2, [sp, #8]
; CHECK-NEXT:    str x3, [sp]
; CHECK-NEXT:    ldrb w8, [sp, #15]
; CHECK-NEXT:    strh w8, [sp, #12]
; CHECK-NEXT:    ldrh w8, [sp, #12]
; CHECK-NEXT:    str w8, [sp, #8]
; CHECK-NEXT:    ldr w8, [sp, #8]
; CHECK-NEXT:    ; kill: def $x8 killed $w8
; CHECK-NEXT:    str x8, [sp]
; CHECK-NEXT:    ldr x0, [sp]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
entry:
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, ptr %a.addr, align 1
  store i16 %b, ptr %b.addr, align 2
  store i32 %c, ptr %c.addr, align 4
  store i64 %d, ptr %d.addr, align 8
  %tmp = load i8, ptr %a.addr, align 1
  %conv = zext i8 %tmp to i16
  store i16 %conv, ptr %b.addr, align 2
  %tmp1 = load i16, ptr %b.addr, align 2
  %conv2 = zext i16 %tmp1 to i32
  store i32 %conv2, ptr %c.addr, align 4
  %tmp3 = load i32, ptr %c.addr, align 4
  %conv4 = zext i32 %tmp3 to i64
  store i64 %conv4, ptr %d.addr, align 8
  %tmp5 = load i64, ptr %d.addr, align 8
  ret i64 %tmp5
}

define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
; CHECK-LABEL: zext_i1_i32:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ret
entry:
  %conv = zext i1 %a to i32
  ret i32 %conv;
}

define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
; CHECK-LABEL: zext_i1_i64:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ; kill: def $x0 killed $w0
; CHECK-NEXT:    ret
entry:
  %conv = zext i1 %a to i64
  ret i64 %conv;
}

define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
; CHECK-LABEL: sext_:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    strb w0, [sp, #15]
; CHECK-NEXT:    strh w1, [sp, #12]
; CHECK-NEXT:    str w2, [sp, #8]
; CHECK-NEXT:    str x3, [sp]
; CHECK-NEXT:    ldrsb w8, [sp, #15]
; CHECK-NEXT:    strh w8, [sp, #12]
; CHECK-NEXT:    ldrsh w8, [sp, #12]
; CHECK-NEXT:    str w8, [sp, #8]
; CHECK-NEXT:    ldrsw x8, [sp, #8]
; CHECK-NEXT:    str x8, [sp]
; CHECK-NEXT:    ldr x0, [sp]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
entry:
  %a.addr = alloca i8, align 1
  %b.addr = alloca i16, align 2
  %c.addr = alloca i32, align 4
  %d.addr = alloca i64, align 8
  store i8 %a, ptr %a.addr, align 1
  store i16 %b, ptr %b.addr, align 2
  store i32 %c, ptr %c.addr, align 4
  store i64 %d, ptr %d.addr, align 8
  %tmp = load i8, ptr %a.addr, align 1
  %conv = sext i8 %tmp to i16
  store i16 %conv, ptr %b.addr, align 2
  %tmp1 = load i16, ptr %b.addr, align 2
  %conv2 = sext i16 %tmp1 to i32
  store i32 %conv2, ptr %c.addr, align 4
  %tmp3 = load i32, ptr %c.addr, align 4
  %conv4 = sext i32 %tmp3 to i64
  store i64 %conv4, ptr %d.addr, align 8
  %tmp5 = load i64, ptr %d.addr, align 8
  ret i64 %tmp5
}

; Test sext i8 to i64

define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
; CHECK-LABEL: sext_i8_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    sxtb x0, w8
; CHECK-NEXT:    ret
  %big = sext i8 %in to i64
  ret i64 %big
}

define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: sext_i16_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    sxth x0, w8
; CHECK-NEXT:    ret
  %big = sext i16 %in to i64
  ret i64 %big
}

; Test sext i1 to i32
define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
; CHECK-LABEL: sext_i1_i32:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ret
entry:
  %conv = sext i1 %a to i32
  ret i32 %conv
}

; Test sext i1 to i16
define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
; CHECK-LABEL: sext_i1_i16:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sbfx w8, w0, #0, #1
; CHECK-NEXT:    sxth w0, w8
; CHECK-NEXT:    ret
entry:
  %conv = sext i1 %a to i16
  ret i16 %conv
}

; Test sext i1 to i8
define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
; CHECK-LABEL: sext_i1_i8:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sbfx w8, w0, #0, #1
; CHECK-NEXT:    sxtb w0, w8
; CHECK-NEXT:    ret
entry:
  %conv = sext i1 %a to i8
  ret i8 %conv
}

; Test fpext
define double @fpext_(float %a) nounwind ssp {
; CHECK-LABEL: fpext_:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvt d0, s0
; CHECK-NEXT:    ret
entry:
  %conv = fpext float %a to double
  ret double %conv
}

; Test fptrunc
define float @fptrunc_(double %a) nounwind ssp {
; CHECK-LABEL: fptrunc_:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvt s0, d0
; CHECK-NEXT:    ret
entry:
  %conv = fptrunc double %a to float
  ret float %conv
}

; Test fptosi
define i32 @fptosi_ws(float %a) nounwind ssp {
; CHECK-LABEL: fptosi_ws:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvtzs w0, s0
; CHECK-NEXT:    ret
entry:
  %conv = fptosi float %a to i32
  ret i32 %conv
}

; Test fptosi
define i32 @fptosi_wd(double %a) nounwind ssp {
; CHECK-LABEL: fptosi_wd:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvtzs w0, d0
; CHECK-NEXT:    ret
entry:
  %conv = fptosi double %a to i32
  ret i32 %conv
}

; Test fptoui
define i32 @fptoui_ws(float %a) nounwind ssp {
; CHECK-LABEL: fptoui_ws:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvtzu w0, s0
; CHECK-NEXT:    ret
entry:
  %conv = fptoui float %a to i32
  ret i32 %conv
}

; Test fptoui
define i32 @fptoui_wd(double %a) nounwind ssp {
; CHECK-LABEL: fptoui_wd:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    fcvtzu w0, d0
; CHECK-NEXT:    ret
entry:
  %conv = fptoui double %a to i32
  ret i32 %conv
}

; Test sitofp
define float @sitofp_sw_i1(i1 %a) nounwind ssp {
; CHECK-LABEL: sitofp_sw_i1:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sbfx w8, w0, #0, #1
; CHECK-NEXT:    scvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i1 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw_i8(i8 %a) nounwind ssp {
; CHECK-LABEL: sitofp_sw_i8:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sxtb w8, w0
; CHECK-NEXT:    scvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i8 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw_i16(i16 %a) nounwind ssp {
; CHECK-LABEL: sitofp_sw_i16:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    sxth w8, w0
; CHECK-NEXT:    scvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i16 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sw(i32 %a) nounwind ssp {
; CHECK-LABEL: sitofp_sw:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    scvtf s0, w0
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i32 %a to float
  ret float %conv
}

; Test sitofp
define float @sitofp_sx(i64 %a) nounwind ssp {
; CHECK-LABEL: sitofp_sx:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    scvtf s0, x0
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i64 %a to float
  ret float %conv
}

; Test sitofp
define double @sitofp_dw(i32 %a) nounwind ssp {
; CHECK-LABEL: sitofp_dw:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    scvtf d0, w0
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i32 %a to double
  ret double %conv
}

; Test sitofp
define double @sitofp_dx(i64 %a) nounwind ssp {
; CHECK-LABEL: sitofp_dx:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    scvtf d0, x0
; CHECK-NEXT:    ret
entry:
  %conv = sitofp i64 %a to double
  ret double %conv
}

; Test uitofp
define float @uitofp_sw_i1(i1 %a) nounwind ssp {
; CHECK-LABEL: uitofp_sw_i1:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    and w8, w0, #0x1
; CHECK-NEXT:    ucvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i1 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw_i8(i8 %a) nounwind ssp {
; CHECK-LABEL: uitofp_sw_i8:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    uxtb w8, w0
; CHECK-NEXT:    ucvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i8 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw_i16(i16 %a) nounwind ssp {
; CHECK-LABEL: uitofp_sw_i16:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    uxth w8, w0
; CHECK-NEXT:    ucvtf s0, w8
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i16 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sw(i32 %a) nounwind ssp {
; CHECK-LABEL: uitofp_sw:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ucvtf s0, w0
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i32 %a to float
  ret float %conv
}

; Test uitofp
define float @uitofp_sx(i64 %a) nounwind ssp {
; CHECK-LABEL: uitofp_sx:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ucvtf s0, x0
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i64 %a to float
  ret float %conv
}

; Test uitofp
define double @uitofp_dw(i32 %a) nounwind ssp {
; CHECK-LABEL: uitofp_dw:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ucvtf d0, w0
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i32 %a to double
  ret double %conv
}

; Test uitofp
define double @uitofp_dx(i64 %a) nounwind ssp {
; CHECK-LABEL: uitofp_dx:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ucvtf d0, x0
; CHECK-NEXT:    ret
entry:
  %conv = uitofp i64 %a to double
  ret double %conv
}

define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
; CHECK-LABEL: i64_trunc_i32:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT:    ret
entry:
  %conv = trunc i64 %a to i32
  ret i32 %conv
}

define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
; CHECK-LABEL: i64_trunc_i16:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    and w8, w8, #0xffff
; CHECK-NEXT:    uxth w0, w8
; CHECK-NEXT:    ret
entry:
  %conv = trunc i64 %a to i16
  ret i16 %conv
}

define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
; CHECK-LABEL: i64_trunc_i8:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    and w8, w8, #0xff
; CHECK-NEXT:    uxtb w0, w8
; CHECK-NEXT:    ret
entry:
  %conv = trunc i64 %a to i8
  ret i8 %conv
}

define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
; CHECK-LABEL: i64_trunc_i1:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    and w8, w8, #0x1
; CHECK-NEXT:    and w0, w8, #0x1
; CHECK-NEXT:    ret
entry:
  %conv = trunc i64 %a to i1
  ret i1 %conv
}

; rdar://15101939
define void @stack_trunc() nounwind {
; CHECK-LABEL: stack_trunc:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    ldr x8, [sp]
; CHECK-NEXT:    ; kill: def $w8 killed $w8 killed $x8
; CHECK-NEXT:    and w8, w8, #0xff
; CHECK-NEXT:    strb w8, [sp, #15]
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
  %a = alloca i8, align 1
  %b = alloca i64, align 8
  %c = load i64, ptr %b, align 8
  %d = trunc i64 %c to i8
  store i8 %d, ptr %a, align 1
  ret void
}

define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
; CHECK-LABEL: zext_i8_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ; kill: def $x0 killed $w0
; CHECK-NEXT:    ret
  %big = zext i8 %in to i64
  ret i64 %big
}
define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
; CHECK-LABEL: zext_i16_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ; kill: def $x0 killed $w0
; CHECK-NEXT:    ret
  %big = zext i16 %in to i64
  ret i64 %big
}

define float @bitcast_i32_to_float(i32 %a) {
; CHECK-LABEL: bitcast_i32_to_float:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    ret
  %1 = bitcast i32 %a to float
  ret float %1
}

define double @bitcast_i64_to_double(i64 %a) {
; CHECK-LABEL: bitcast_i64_to_double:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    ret
  %1 = bitcast i64 %a to double
  ret double %1
}

define i32 @bitcast_float_to_i32(float %a) {
; CHECK-LABEL: bitcast_float_to_i32:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    fmov w0, s0
; CHECK-NEXT:    ret
  %1 = bitcast float %a to i32
  ret i32 %1
}

define i64 @bitcast_double_to_i64(double %a) {
; CHECK-LABEL: bitcast_double_to_i64:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    fmov x0, d0
; CHECK-NEXT:    ret
  %1 = bitcast double %a to i64
  ret i64 %1
}