llvm/test/CodeGen/AArch64/alias_mask_nosve.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s

; TODO: Currently lowering get_active_lane_mask requires +sve
; XFAIL: *

define <16 x i1> @whilewr_8(i64 %a, i64 %b) {
entry:
  %0 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1.i64(i64 %a, i64 %b, i64 1)
  ret <16 x i1> %0
}