| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null -verify-machineinstrs --run-pass=amdgpu-print-rp %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPU |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --filetype=null -verify-machineinstrs --run-pass=amdgpu-print-rp -amdgpu-print-rp-downward %s 2>&1 >/dev/null | FileCheck %s --check-prefix=RP --check-prefix=RPD |
| |
| |
| --- |
| name: trivial |
| tracksRegLiveness: true |
| body: | |
| ; RP-LABEL: name: trivial |
| ; RP: bb.0: |
| ; RP-NEXT: Live-in: |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: 0 1 %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| ; RP-NEXT: 0 1 |
| ; RP-NEXT: 2 1 %1:sgpr_64 = IMPLICIT_DEF |
| ; RP-NEXT: 2 1 |
| ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: bb.1: |
| ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 2 1 |
| ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000F |
| ; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000F |
| ; RP-NEXT: 2 1 |
| ; RP-NEXT: bb.2: |
| ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000F |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 2 1 |
| ; RP-NEXT: 2 1 S_NOP 0, implicit %0:vgpr_32, implicit %1:sgpr_64 |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: Live-out: |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| bb.0: |
| %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| %1:sgpr_64 = IMPLICIT_DEF |
| bb.1: |
| |
| bb.2: |
| S_NOP 0, implicit %0, implicit %1 |
| ... |
| --- |
| name: live_through_test |
| tracksRegLiveness: true |
| body: | |
| ; RP-LABEL: name: live_through_test |
| ; RP: bb.0: |
| ; RP-NEXT: Live-in: |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: 4 0 %0:sgpr_128 = IMPLICIT_DEF |
| ; RP-NEXT: 3 0 |
| ; RP-NEXT: Live-out: %0:00000000000000F3 |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: bb.1: |
| ; RP-NEXT: Live-in: %0:00000000000000F3 |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 3 0 |
| ; RP-NEXT: 3 0 S_NOP 0, implicit %0.sub0:sgpr_128 |
| ; RP-NEXT: 2 0 |
| ; RP-NEXT: 3 0 %0.sub0:sgpr_128 = IMPLICIT_DEF |
| ; RP-NEXT: 3 0 |
| ; RP-NEXT: 4 0 %0.sub1:sgpr_128 = IMPLICIT_DEF |
| ; RP-NEXT: 3 0 |
| ; RP-NEXT: 3 0 S_NOP 0, implicit %0.sub2:sgpr_128 |
| ; RP-NEXT: 2 0 |
| ; RP-NEXT: 3 0 %0.sub2:sgpr_128 = IMPLICIT_DEF |
| ; RP-NEXT: 3 0 |
| ; RP-NEXT: 3 0 S_NOP 0, implicit %0.sub2:sgpr_128 |
| ; RP-NEXT: 2 0 |
| ; RP-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128 |
| ; RP-NEXT: 2 0 |
| ; RP-NEXT: Live-out: %0:00000000000000C3 |
| ; RP-NEXT: Live-thr: %0:00000000000000C0 |
| ; RP-NEXT: 1 0 |
| ; RP-NEXT: bb.2: |
| ; RP-NEXT: Live-in: %0:00000000000000C3 |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 2 0 |
| ; RP-NEXT: 2 0 S_NOP 0, implicit %0.sub3:sgpr_128, implicit %0.sub0:sgpr_128 |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: Live-out: |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| bb.0: |
| %0:sgpr_128 = IMPLICIT_DEF |
| bb.1: |
| |
| S_NOP 0, implicit %0.sub0 ; kill sub0 |
| %0.sub0 = IMPLICIT_DEF ; redef sub0 |
| |
| %0.sub1:sgpr_128 = IMPLICIT_DEF ; redef sub1 |
| |
| S_NOP 0, implicit %0.sub2 ; kill sub2 |
| %0.sub2:sgpr_128 = IMPLICIT_DEF ; redef sub2 |
| S_NOP 0, implicit %0.sub2 ; kill sub2 |
| |
| S_NOP 0, implicit %0.sub3 ; use sub3, live-through |
| |
| bb.2: |
| S_NOP 0, implicit %0.sub3, implicit %0.sub0 |
| ... |
| |
| # This testcase shows the problem with LiveIntervals: it doesn't create |
| # subranges for undefined but used subregisters. Upward tracker is able to see |
| # the use of undefined subregister and tracks it correctly. |
| --- |
| name: upward_problem_lis_subregs_mismatch |
| tracksRegLiveness: true |
| body: | |
| ; RP-LABEL: name: upward_problem_lis_subregs_mismatch |
| ; RP: bb.0: |
| ; RP-NEXT: Live-in: |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: 0 1 undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec |
| ; RP-NEXT: 0 1 |
| ; RP-NEXT: 0 2 undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec |
| ; RP-NEXT: 0 2 |
| ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: bb.1: |
| ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 2 |
| ; RP-NEXT: Live-out: %0:0000000000000003 %1:000000000000000C |
| ; RP-NEXT: Live-thr: %0:0000000000000003 %1:000000000000000C |
| ; RP-NEXT: 0 2 |
| ; RP-NEXT: bb.2: |
| ; RP-NEXT: Live-in: %0:0000000000000003 %1:000000000000000C |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 2 |
| ; RP-NEXT: 0 2 S_NOP 0, implicit %0:vreg_64, implicit %1:vreg_64 |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: Live-out: |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| bb.0: |
| undef %0.sub0:vreg_64 = V_MOV_B32_e32 42, implicit $exec |
| undef %1.sub1:vreg_64 = V_MOV_B32_e32 33, implicit $exec |
| |
| bb.1: |
| |
| bb.2: |
| S_NOP 0, implicit %0, implicit %1 |
| ... |
| --- |
| name: only_dbg_value_sched_region |
| tracksRegLiveness: true |
| machineFunctionInfo: |
| isEntryFunction: true |
| waveLimiter: true |
| body: | |
| ; RPU-LABEL: name: only_dbg_value_sched_region |
| ; RPU: bb.0: |
| ; RPU-NEXT: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 1 %0:vgpr_32 = COPY $vgpr0 |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 3 %1:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 3 |
| ; RPU-NEXT: 0 5 %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 5 |
| ; RPU-NEXT: 0 6 %3:vgpr_32 = GLOBAL_LOAD_DWORD %1:vreg_64, 8, 0, implicit $exec |
| ; RPU-NEXT: 0 6 |
| ; RPU-NEXT: 0 7 undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0:vgpr_32, %0:vgpr_32, implicit $exec |
| ; RPU-NEXT: 0 7 |
| ; RPU-NEXT: 0 8 %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec |
| ; RPU-NEXT: 0 8 |
| ; RPU-NEXT: 0 9 %5:vreg_64 = COPY %2:vreg_64 |
| ; RPU-NEXT: 0 9 |
| ; RPU-NEXT: 0 9 undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0:vreg_64, %5.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPU-NEXT: 0 8 |
| ; RPU-NEXT: 0 8 dead %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1:vreg_64, %5.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPU-NEXT: 0 7 |
| ; RPU-NEXT: 0 7 %7:vgpr_32 = GLOBAL_LOAD_DWORD %5:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 6 |
| ; RPU-NEXT: 0 8 %8:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 7 |
| ; RPU-NEXT: 0 9 %9:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 9 |
| ; RPU-NEXT: 0 11 %10:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 11 |
| ; RPU-NEXT: 0 12 undef %11.sub1:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 12 |
| ; RPU-NEXT: 0 13 %12:vgpr_32 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 13 |
| ; RPU-NEXT: 0 14 %13:vgpr_32 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 14 |
| ; RPU-NEXT: 0 16 %14:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 16 |
| ; RPU-NEXT: 0 18 %15:vreg_64 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 18 |
| ; RPU-NEXT: 0 19 %16:vgpr_32 = IMPLICIT_DEF |
| ; RPU-NEXT: 0 19 |
| ; RPU-NEXT: 0 20 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; RPU-NEXT: 0 20 |
| ; RPU-NEXT: 0 21 %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; RPU-NEXT: 0 21 |
| ; RPU-NEXT: 0 21 undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7:vgpr_32, %2.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPU-NEXT: 0 20 |
| ; RPU-NEXT: 0 20 %19.sub1:vreg_64 = V_ADD_F32_e32 %3:vgpr_32, %3:vgpr_32, implicit $mode, implicit $exec |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: 0 20 |
| ; RPU-NEXT: 0 20 GLOBAL_STORE_DWORDX2 %19:vreg_64, %4:vreg_64, 32, 0, implicit $exec |
| ; RPU-NEXT: 0 16 |
| ; RPU-NEXT: 0 16 %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 15 |
| ; RPU-NEXT: 0 15 %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 14 |
| ; RPU-NEXT: 0 14 dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: 0 12 |
| ; RPU-NEXT: 0 12 dead %21:vgpr_32 = GLOBAL_LOAD_DWORD %14:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 10 |
| ; RPU-NEXT: 0 11 dead %22:vgpr_32 = GLOBAL_LOAD_DWORD %15:vreg_64, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 10 |
| ; RPU-NEXT: 0 10 %23:vreg_64 = V_LSHLREV_B64_e64 2, %8:vreg_64, implicit $exec |
| ; RPU-NEXT: 0 9 |
| ; RPU-NEXT: 0 9 S_NOP 0, implicit %13:vgpr_32, implicit %23.sub0:vreg_64, implicit %12:vgpr_32, implicit %17:vgpr_32 |
| ; RPU-NEXT: 0 5 |
| ; RPU-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: bb.1: |
| ; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: 0 2 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: 0 2 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| ; RPU-NEXT: DBG_VALUE |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: bb.2: |
| ; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: bb.3: |
| ; RPU-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 2 |
| ; RPU-NEXT: 0 2 S_NOP 0, implicit %0:vgpr_32 |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 S_NOP 0, implicit %16:vgpr_32 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 S_ENDPGM 0 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; |
| ; RPD-LABEL: name: only_dbg_value_sched_region |
| ; RPD: bb.0: |
| ; RPD-NEXT: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 1 %0:vgpr_32 = COPY $vgpr0 |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 3 %1:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 3 |
| ; RPD-NEXT: 0 5 %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 5 |
| ; RPD-NEXT: 0 6 %3:vgpr_32 = GLOBAL_LOAD_DWORD %1:vreg_64, 8, 0, implicit $exec |
| ; RPD-NEXT: 0 6 |
| ; RPD-NEXT: 0 7 undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0:vgpr_32, %0:vgpr_32, implicit $exec |
| ; RPD-NEXT: 0 7 |
| ; RPD-NEXT: 0 8 %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec |
| ; RPD-NEXT: 0 8 |
| ; RPD-NEXT: 0 10 %5:vreg_64 = COPY %2:vreg_64 |
| ; RPD-NEXT: 0 9 |
| ; RPD-NEXT: 0 10 undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0:vreg_64, %5.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPD-NEXT: 0 8 |
| ; RPD-NEXT: 0 9 dead %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1:vreg_64, %5.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPD-NEXT: 0 7 |
| ; RPD-NEXT: 0 8 %7:vgpr_32 = GLOBAL_LOAD_DWORD %5:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 6 |
| ; RPD-NEXT: 0 8 %8:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 7 |
| ; RPD-NEXT: 0 9 %9:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 9 |
| ; RPD-NEXT: 0 11 %10:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 11 |
| ; RPD-NEXT: 0 12 undef %11.sub1:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 12 |
| ; RPD-NEXT: 0 13 %12:vgpr_32 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 13 |
| ; RPD-NEXT: 0 14 %13:vgpr_32 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 14 |
| ; RPD-NEXT: 0 16 %14:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 16 |
| ; RPD-NEXT: 0 18 %15:vreg_64 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 18 |
| ; RPD-NEXT: 0 19 %16:vgpr_32 = IMPLICIT_DEF |
| ; RPD-NEXT: 0 19 |
| ; RPD-NEXT: 0 20 %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; RPD-NEXT: 0 20 |
| ; RPD-NEXT: 0 21 %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| ; RPD-NEXT: 0 21 |
| ; RPD-NEXT: 0 22 undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7:vgpr_32, %2.sub0:vreg_64, implicit $mode, implicit $exec |
| ; RPD-NEXT: 0 20 |
| ; RPD-NEXT: 0 21 %19.sub1:vreg_64 = V_ADD_F32_e32 %3:vgpr_32, %3:vgpr_32, implicit $mode, implicit $exec |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: 0 20 |
| ; RPD-NEXT: 0 20 GLOBAL_STORE_DWORDX2 %19:vreg_64, %4:vreg_64, 32, 0, implicit $exec |
| ; RPD-NEXT: 0 16 |
| ; RPD-NEXT: 0 17 %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 15 |
| ; RPD-NEXT: 0 16 %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 14 |
| ; RPD-NEXT: 0 15 dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: 0 12 |
| ; RPD-NEXT: 0 13 dead %21:vgpr_32 = GLOBAL_LOAD_DWORD %14:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 10 |
| ; RPD-NEXT: 0 11 dead %22:vgpr_32 = GLOBAL_LOAD_DWORD %15:vreg_64, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 10 |
| ; RPD-NEXT: 0 12 %23:vreg_64 = V_LSHLREV_B64_e64 2, %8:vreg_64, implicit $exec |
| ; RPD-NEXT: 0 9 |
| ; RPD-NEXT: 0 9 S_NOP 0, implicit %13:vgpr_32, implicit %23.sub0:vreg_64, implicit %12:vgpr_32, implicit %17:vgpr_32 |
| ; RPD-NEXT: 0 5 |
| ; RPD-NEXT: 0 5 GLOBAL_STORE_DWORD %15:vreg_64, %18:vgpr_32, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: bb.1: |
| ; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: 0 2 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: 0 2 S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| ; RPD-NEXT: DBG_VALUE |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: bb.2: |
| ; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: Live-out: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: Live-thr: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: bb.3: |
| ; RPD-NEXT: Live-in: %0:0000000000000003 %16:0000000000000003 |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 2 |
| ; RPD-NEXT: 0 2 S_NOP 0, implicit %0:vgpr_32 |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 S_NOP 0, implicit %16:vgpr_32 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 S_ENDPGM 0 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: Live-out: |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| bb.0: |
| liveins: $vgpr0 |
| |
| %0:vgpr_32 = COPY $vgpr0 |
| %1:vreg_64 = IMPLICIT_DEF |
| %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, implicit $exec |
| %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, implicit $exec |
| undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec |
| %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec |
| %5:vreg_64 = COPY %2 |
| undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $mode, implicit $exec |
| %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $mode, implicit $exec |
| %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, implicit $exec |
| %8:vreg_64 = IMPLICIT_DEF |
| %9:vreg_64 = IMPLICIT_DEF |
| %10:vreg_64 = IMPLICIT_DEF |
| undef %11.sub1:vreg_64 = IMPLICIT_DEF |
| %12:vgpr_32 = IMPLICIT_DEF |
| %13:vgpr_32 = IMPLICIT_DEF |
| %14:vreg_64 = IMPLICIT_DEF |
| %15:vreg_64 = IMPLICIT_DEF |
| %16:vgpr_32 = IMPLICIT_DEF |
| %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec |
| undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $mode, implicit $exec |
| %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $mode, implicit $exec |
| DBG_VALUE |
| GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, implicit $exec |
| %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, implicit $exec |
| %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, implicit $exec |
| %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, implicit $exec |
| DBG_VALUE |
| DBG_VALUE |
| %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, implicit $exec |
| %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, implicit $exec |
| %23:vreg_64 = V_LSHLREV_B64_e64 2, %8, implicit $exec |
| S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17 |
| GLOBAL_STORE_DWORD %15, %18, 0, 0, implicit $exec |
| |
| bb.1: |
| DBG_VALUE |
| S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| DBG_VALUE |
| DBG_VALUE |
| S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode |
| DBG_VALUE |
| |
| bb.3: |
| |
| bb.2: |
| S_NOP 0, implicit %0 |
| S_NOP 0, implicit %16 |
| S_ENDPGM 0 |
| ... |
| --- |
| name: test_early_clobber_trivial |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; RP-LABEL: name: test_early_clobber_trivial |
| ; RP: Live-in: |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: 0 1 %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| ; RP-NEXT: 0 1 |
| ; RP-NEXT: 0 2 early-clobber %1:vgpr_32 = V_MOV_B32_e32 %0:vgpr_32, implicit $exec |
| ; RP-NEXT: 0 1 |
| ; RP-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32 |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: Live-out: |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| early-clobber %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec |
| S_NOP 0, implicit %1 |
| ... |
| --- |
| name: test_not_early_clobber_trivial |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| ; RPU-LABEL: name: test_not_early_clobber_trivial |
| ; RPU: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 1 %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 %1:vgpr_32 = V_MOV_B32_e32 %0:vgpr_32, implicit $exec |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; |
| ; RPD-LABEL: name: test_not_early_clobber_trivial |
| ; RPD: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 1 %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 2 %1:vgpr_32 = V_MOV_B32_e32 %0:vgpr_32, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 S_NOP 0, implicit %1:vgpr_32 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: Live-out: |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| %0:vgpr_32 = V_MOV_B32_e32 42, implicit $exec |
| %1:vgpr_32 = V_MOV_B32_e32 %0, implicit $exec |
| S_NOP 0, implicit %1 |
| ... |
| --- |
| name: movrel |
| tracksRegLiveness: true |
| body: | |
| ; RPU-LABEL: name: movrel |
| ; RPU: bb.0: |
| ; RPU-NEXT: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 $sgpr0 = COPY $sgpr1 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 S_BRANCH %bb.1 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: bb.1: |
| ; RPU-NEXT: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0 |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 16 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: Live-out: %0:0000000000000C00 |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: bb.2: |
| ; RPU-NEXT: Live-in: %0:0000000000000C00 |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec |
| ; RPU-NEXT: 0 1 |
| ; RPU-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 0 0 S_ENDPGM 0 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; |
| ; RPD-LABEL: name: movrel |
| ; RPD: bb.0: |
| ; RPD-NEXT: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 $sgpr0 = COPY $sgpr1 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 $sgpr2_sgpr3 = S_GETPC_B64 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 $sgpr1 = COPY killed $sgpr3 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM $sgpr0_sgpr1, 0, 0 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 $sgpr0 = S_BUFFER_LOAD_DWORD_IMM $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 S_BRANCH %bb.1 |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: Live-out: %0:0000000000000C00 |
| ; RPD-NEXT: mis LIS: |
| ; RPD-NEXT: %0:L0000000000000C00 isn't found in LIS reported set |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: bb.1: |
| ; RPD-NEXT: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 1 undef %0.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 $m0 = S_MOV_B32 killed $sgpr0 |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 16 %0:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %0:vreg_512(tied-def 0), 42, 3, implicit $m0, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: Live-out: %0:0000000000000C00 |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: bb.2: |
| ; RPD-NEXT: Live-in: %0:0000000000000C00 |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 2 %1:vgpr_32 = V_CVT_F32_UBYTE0_e64 %0.sub5:vreg_512, 0, 0, implicit $exec |
| ; RPD-NEXT: 0 1 |
| ; RPD-NEXT: 0 1 EXP_DONE 0, %1:vgpr_32, undef %2:vgpr_32, undef %3:vgpr_32, undef %4:vgpr_32, -1, 0, 1, implicit $exec |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 0 0 S_ENDPGM 0 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: Live-out: |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| bb.0: |
| liveins: $sgpr1 |
| $sgpr0 = COPY $sgpr1 |
| $sgpr2_sgpr3 = S_GETPC_B64 |
| $sgpr1 = COPY killed $sgpr3 |
| $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed $sgpr0_sgpr1, 0, 0 |
| $sgpr0 = S_BUFFER_LOAD_DWORD_IMM killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0 |
| undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| S_CMP_GT_U32 $sgpr0, 15, implicit-def $scc |
| S_CBRANCH_SCC1 %bb.2, implicit $scc |
| S_BRANCH %bb.1 |
| |
| bb.1: |
| liveins: $sgpr0 |
| undef %47.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec |
| $m0 = S_MOV_B32 killed $sgpr0 |
| %47:vreg_512 = V_INDIRECT_REG_WRITE_MOVREL_B32_V16 %47:vreg_512, 42, 3, implicit $m0, implicit $exec |
| |
| bb.2: |
| |
| %49:vgpr_32 = V_CVT_F32_UBYTE0_e64 %47.sub5:vreg_512, 0, 0, implicit $exec |
| EXP_DONE 0, %49:vgpr_32, undef %51:vgpr_32, undef %53:vgpr_32, undef %55:vgpr_32, -1, 0, 1, implicit $exec |
| S_ENDPGM 0 |
| ... |
| --- |
| name: test_partially_used_def |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPU-LABEL: name: test_partially_used_def |
| ; RPU: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPU-NEXT: 4 0 |
| ; RPU-NEXT: 4 0 %1:sgpr_128 = COPY %0:sgpr_128 |
| ; RPU-NEXT: 1 0 |
| ; RPU-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; |
| ; RPD-LABEL: name: test_partially_used_def |
| ; RPD: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPD-NEXT: 4 0 |
| ; RPD-NEXT: 8 0 %1:sgpr_128 = COPY %0:sgpr_128 |
| ; RPD-NEXT: 1 0 |
| ; RPD-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: Live-out: |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| %1:sgpr_128 = COPY %0:sgpr_128 |
| S_NOP 0, implicit %1.sub1 |
| ... |
| --- |
| name: test_partially_used_early_clobber_def |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RP-LABEL: name: test_partially_used_early_clobber_def |
| ; RP: Live-in: |
| ; RP-NEXT: SGPR VGPR |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RP-NEXT: 4 0 |
| ; RP-NEXT: 8 0 early-clobber %1:sgpr_128 = COPY %0:sgpr_128 |
| ; RP-NEXT: 1 0 |
| ; RP-NEXT: 1 0 S_NOP 0, implicit %1.sub1:sgpr_128 |
| ; RP-NEXT: 0 0 |
| ; RP-NEXT: Live-out: |
| ; RP-NEXT: Live-thr: |
| ; RP-NEXT: 0 0 |
| %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| early-clobber %1:sgpr_128 = COPY %0:sgpr_128 |
| S_NOP 0, implicit %1.sub1 |
| ... |
| --- |
| name: test_partially_used_def_and_early_clobber_def |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPU-LABEL: name: test_partially_used_def_and_early_clobber_def |
| ; RPU: Live-in: |
| ; RPU-NEXT: SGPR VGPR |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPU-NEXT: 4 0 |
| ; RPU-NEXT: 16 0 %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def dead early-clobber %4:sgpr_128 |
| ; RPU-NEXT: 6 0 |
| ; RPU-NEXT: 6 0 S_NOP 0, implicit %1.sub1:sgpr_128, implicit %2.sub0_sub1:sgpr_128, implicit %3.sub0_sub1_sub2:sgpr_128 |
| ; RPU-NEXT: 0 0 |
| ; RPU-NEXT: Live-out: |
| ; RPU-NEXT: Live-thr: |
| ; RPU-NEXT: 0 0 |
| ; |
| ; RPD-LABEL: name: test_partially_used_def_and_early_clobber_def |
| ; RPD: Live-in: |
| ; RPD-NEXT: SGPR VGPR |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: 4 0 %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| ; RPD-NEXT: 4 0 |
| ; RPD-NEXT: 20 0 %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def dead early-clobber %4:sgpr_128 |
| ; RPD-NEXT: 6 0 |
| ; RPD-NEXT: 6 0 S_NOP 0, implicit %1.sub1:sgpr_128, implicit %2.sub0_sub1:sgpr_128, implicit %3.sub0_sub1_sub2:sgpr_128 |
| ; RPD-NEXT: 0 0 |
| ; RPD-NEXT: Live-out: |
| ; RPD-NEXT: Live-thr: |
| ; RPD-NEXT: 0 0 |
| %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3 |
| %1:sgpr_128 = COPY %0:sgpr_128, implicit-def %2:sgpr_128, implicit-def early-clobber %3:sgpr_128, implicit-def early-clobber %4:sgpr_128 |
| S_NOP 0, implicit %1.sub1, implicit %2.sub0_sub1, implicit %3.sub0_sub1_sub2 |
| ... |
