[RISCV][P-ext] Add codegen for packed reduction sum (#206004) The predsum/predsumu instructions reduce a packed vector to a scalar: each element is sign- or zero-extended to the accumulator width and added to the scalar accumulator rs2. This patch adds the llvm.riscv.predsum and predsumu intrinsics along with isel patterns for target-legal results (predsum.bs/hs/ws, plus the paired predsum.dbs/dhs for a GPRPair source on RV32). The remaining combinations have a target-illegal result and are split in ReplaceNodeResults: * On RV64: An i32 accumulator reduces at i64 and is then truncated (the 32-bit source is zero-extended first). * On RV32: An i64 accumulator reduces to a 32-bit partial sum and is widening-accumulated via wadda/waddau.
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