)]}'
{
  "commit": "eb29d7f2773b64e3bc8a6804db44bc45dfecb032",
  "tree": "e0c9a7f0d0f4bcb058fe377115fb53873cb294d0",
  "parents": [
    "acf21896447b2eaecb8f62d94d8dbec1f2860ad3"
  ],
  "author": {
    "name": "SiHuaN",
    "email": "liyongtai@iscas.ac.cn",
    "time": "Mon Jun 29 15:11:22 2026 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jun 29 15:11:22 2026 +0800"
  },
  "message": "[RISCV][P-ext] Add codegen for packed reduction sum (#206004)\n\nThe predsum/predsumu instructions reduce a packed vector to a scalar:\neach element is sign- or zero-extended to the accumulator width and\nadded to the scalar accumulator rs2.\n\nThis patch adds the llvm.riscv.predsum and predsumu intrinsics along\nwith isel patterns for target-legal results (predsum.bs/hs/ws, plus\nthe paired predsum.dbs/dhs for a GPRPair source on RV32).\n\nThe remaining combinations have a target-illegal result and are split\nin ReplaceNodeResults:\n* On RV64: An i32 accumulator reduces at i64 and is then truncated\n  (the 32-bit source is zero-extended first).\n* On RV32: An i64 accumulator reduces to a 32-bit partial sum and is\n  widening-accumulated via wadda/waddau.",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/include/llvm/IR/IntrinsicsRISCV.td",
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      "new_mode": 33188,
      "new_path": "llvm/include/llvm/IR/IntrinsicsRISCV.td"
    },
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      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVISelLowering.cpp"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVInstrInfoP.td",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVInstrInfoP.td"
    },
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      "type": "modify",
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      "new_path": "llvm/test/CodeGen/RISCV/rvp-simd-32.ll"
    },
    {
      "type": "modify",
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}