llvm/test/Transforms/SLPVectorizer/X86/parent-non-schedule-multi-use-in-binop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=slp-vectorizer -S --mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

@a = common global [100 x i64] zeroinitializer, align 64

define void @test() {
; CHECK-LABEL: define void @test() {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i64>, ptr getelementptr inbounds nuw (i8, ptr @a, i64 48), align 8
; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i64> [[TMP0]], splat (i64 1)
; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i64> [[TMP2]], splat (i64 1)
; CHECK-NEXT:    br i1 false, label %[[LOP_RHSCNT_I_PEEL:.*]], label %[[LAND_END_I_PEEL:.*]]
; CHECK:       [[LOP_RHSCNT_I_PEEL]]:
; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i64> [[TMP1]], <i64 1, i64 0>
; CHECK-NEXT:    br label %[[LAND_END_I_PEEL]]
; CHECK:       [[LAND_END_I_PEEL]]:
; CHECK-NEXT:    [[TMP5:%.*]] = phi <2 x i64> [ [[TMP3]], %[[ENTRY]] ], [ [[TMP4]], %[[LOP_RHSCNT_I_PEEL]] ]
; CHECK-NEXT:    store <2 x i64> [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @a, i64 48), align 8
; CHECK-NEXT:    ret void
;
entry:
  %.promoted104.i = load i64, ptr getelementptr inbounds nuw (i8, ptr @a, i64 56), align 8
  %.promoted103.i = load i64, ptr getelementptr inbounds nuw (i8, ptr @a, i64 48), align 8
  %0 = add i64 %.promoted104.i, 1
  %1 = add i64 %.promoted103.i, 1
  %2 = add i64 %0, 1
  br i1 false, label %lop.rhscnt.i.peel, label %land.end.i.peel

lop.rhscnt.i.peel:
  %3 = or i64 %1, 1
  br label %land.end.i.peel

land.end.i.peel:
  %4 = phi i64 [ %2, %entry ], [ %0, %lop.rhscnt.i.peel ]
  %5 = phi i64 [ %1, %entry ], [ %3, %lop.rhscnt.i.peel ]
  store i64 %5, ptr getelementptr inbounds nuw (i8, ptr @a, i64 48), align 8
  store i64 %4, ptr getelementptr inbounds nuw (i8, ptr @a, i64 56), align 8
  ret void
}