llvm/test/CodeGen/X86/pr27202.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

define i1 @foo(i32 %i) optsize {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl $305419896, %eax # imm = 0x12345678
; CHECK-NEXT:    andl %eax, %edi
; CHECK-NEXT:    cmpl %eax, %edi
; CHECK-NEXT:    sete %al
; CHECK-NEXT:    retq
  %and = and i32 %i, 305419896
  %cmp = icmp eq i32 %and, 305419896
  ret i1 %cmp
}

; 8-bit ALU immediates probably have small encodings.
; We do not want to hoist the constant into a register here.

define zeroext i1 @g(i32 %x) optsize {
; CHECK-LABEL: g:
; CHECK:       # %bb.0:
; CHECK-NEXT:    orl $1, %edi
; CHECK-NEXT:    cmpl $1, %edi
; CHECK-NEXT:    sete %al
; CHECK-NEXT:    retq
  %t0 = or i32 %x, 1
  %t1 = icmp eq i32 %t0, 1
  ret i1 %t1
}

; 8-bit ALU immediates probably have small encodings.
; We do not want to hoist the constant into a register here.

define i64 @PR46237(i64 %x, i64 %y, i64 %z) optsize {
; CHECK-LABEL: PR46237:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl %edx, %eax
; CHECK-NEXT:    shll $6, %eax
; CHECK-NEXT:    movzbl %al, %ecx
; CHECK-NEXT:    andl $7, %esi
; CHECK-NEXT:    andl $7, %edx
; CHECK-NEXT:    leaq (%rdx,%rsi,8), %rax
; CHECK-NEXT:    orq %rcx, %rax
; CHECK-NEXT:    retq
  %and = shl i64 %z, 6
  %shl = and i64 %and, 192
  %and1 = shl i64 %y, 3
  %shl2 = and i64 %and1, 56
  %and3 = and i64 %z, 7
  %or = or i64 %and3, %shl2
  %or4 = or i64 %or, %shl
  ret i64 %or4
}