llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S | FileCheck --check-prefix=RV64 %s
; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv32 -mattr=+v -S | FileCheck --check-prefix=RV32 %s

define void @narrow_iv_i8_sext_i64(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_sext_i64(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {
; RV64-NEXT:  [[ENTRY:.*:]]
; RV64-NEXT:    br label %[[VECTOR_PH:.*]]
; RV64:       [[VECTOR_PH]]:
; RV64-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV64-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV64-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV64:       [[VECTOR_BODY]]:
; RV64-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV64-NEXT:    [[TMP1:%.*]] = sext i32 [[INDEX]] to i64
; RV64-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP1]], 12
; RV64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP5]]
; RV64-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr align 1 [[TMP2]], i64 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV64-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV64-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV64-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; RV64:       [[MIDDLE_BLOCK]]:
; RV64-NEXT:    br label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret void
;
; RV32-LABEL: define void @narrow_iv_i8_sext_i64(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {
; RV32-NEXT:  [[ENTRY:.*:]]
; RV32-NEXT:    br label %[[VECTOR_PH:.*]]
; RV32:       [[VECTOR_PH]]:
; RV32-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV32-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV32-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV32:       [[VECTOR_BODY]]:
; RV32-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV32-NEXT:    [[TMP1:%.*]] = shl i32 [[INDEX]], 12
; RV32-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i32 [[TMP1]]
; RV32-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr align 1 [[TMP2]], i32 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV32-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV32-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV32-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; RV32:       [[MIDDLE_BLOCK]]:
; RV32-NEXT:    br label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %i = phi i8 [ 0, %entry ], [ %i.next, %loop ]
  %idx = sext i8 %i to i64
  %ptr = getelementptr [1024 x i8], ptr %arr, i64 %idx
  %val = load i8, ptr %ptr, align 1
  store i8 %val, ptr %out, align 1
  %i.next = add i8 %i, 4
  %cmp = icmp ult i8 %i.next, 64
  br i1 %cmp, label %loop, label %exit

exit:
  ret void
}

define void @narrow_iv_i8_sext_i16(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_sext_i16(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV64-NEXT:  [[ENTRY:.*:]]
; RV64-NEXT:    br label %[[VECTOR_PH:.*]]
; RV64:       [[VECTOR_PH]]:
; RV64-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV64-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV64-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV64:       [[VECTOR_BODY]]:
; RV64-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV64-NEXT:    [[TMP1:%.*]] = sext i32 [[INDEX]] to i64
; RV64-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP1]], 12
; RV64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP5]]
; RV64-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr align 1 [[TMP2]], i64 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV64-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV64-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV64-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; RV64:       [[MIDDLE_BLOCK]]:
; RV64-NEXT:    br label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret void
;
; RV32-LABEL: define void @narrow_iv_i8_sext_i16(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV32-NEXT:  [[ENTRY:.*:]]
; RV32-NEXT:    br label %[[VECTOR_PH:.*]]
; RV32:       [[VECTOR_PH]]:
; RV32-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV32-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV32-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV32:       [[VECTOR_BODY]]:
; RV32-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV32-NEXT:    [[TMP1:%.*]] = shl i32 [[INDEX]], 12
; RV32-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i32 [[TMP1]]
; RV32-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr align 1 [[TMP2]], i32 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV32-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV32-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV32-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; RV32:       [[MIDDLE_BLOCK]]:
; RV32-NEXT:    br label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %i = phi i8 [ 0, %entry ], [ %i.next, %loop ]
  %idx = sext i8 %i to i16
  %ptr = getelementptr [1024 x i8], ptr %arr, i16 %idx
  %val = load i8, ptr %ptr, align 1
  store i8 %val, ptr %out, align 1
  %i.next = add i8 %i, 4
  %cmp = icmp ult i8 %i.next, 64
  br i1 %cmp, label %loop, label %exit

exit:
  ret void
}

define void @narrow_iv_i8_zext_i64(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_zext_i64(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV64-NEXT:  [[ENTRY:.*:]]
; RV64-NEXT:    br label %[[VECTOR_PH:.*]]
; RV64:       [[VECTOR_PH]]:
; RV64-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV64-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV64-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV64:       [[VECTOR_BODY]]:
; RV64-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV64-NEXT:    [[TMP1:%.*]] = sext i32 [[INDEX]] to i64
; RV64-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP1]], 12
; RV64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP5]]
; RV64-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr align 1 [[TMP2]], i64 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV64-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV64-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV64-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; RV64:       [[MIDDLE_BLOCK]]:
; RV64-NEXT:    br label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret void
;
; RV32-LABEL: define void @narrow_iv_i8_zext_i64(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV32-NEXT:  [[ENTRY:.*:]]
; RV32-NEXT:    br label %[[VECTOR_PH:.*]]
; RV32:       [[VECTOR_PH]]:
; RV32-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV32-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV32-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV32:       [[VECTOR_BODY]]:
; RV32-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV32-NEXT:    [[TMP1:%.*]] = shl i32 [[INDEX]], 12
; RV32-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i32 [[TMP1]]
; RV32-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr align 1 [[TMP2]], i32 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV32-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV32-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV32-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; RV32:       [[MIDDLE_BLOCK]]:
; RV32-NEXT:    br label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %i = phi i8 [ 0, %entry ], [ %i.next, %loop ]
  %idx = zext i8 %i to i64
  %ptr = getelementptr [1024 x i8], ptr %arr, i64 %idx
  %val = load i8, ptr %ptr, align 1
  store i8 %val, ptr %out, align 1
  %i.next = add i8 %i, 4
  %cmp = icmp ult i8 %i.next, 64
  br i1 %cmp, label %loop, label %exit

exit:
  ret void
}

define void @narrow_iv_i8_zext_i16(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_zext_i16(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV64-NEXT:  [[ENTRY:.*:]]
; RV64-NEXT:    br label %[[VECTOR_PH:.*]]
; RV64:       [[VECTOR_PH]]:
; RV64-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV64-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV64-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV64:       [[VECTOR_BODY]]:
; RV64-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV64-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV64-NEXT:    [[TMP1:%.*]] = sext i32 [[INDEX]] to i64
; RV64-NEXT:    [[TMP5:%.*]] = shl i64 [[TMP1]], 12
; RV64-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP5]]
; RV64-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr align 1 [[TMP2]], i64 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV64-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV64-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV64-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV64-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; RV64:       [[MIDDLE_BLOCK]]:
; RV64-NEXT:    br label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret void
;
; RV32-LABEL: define void @narrow_iv_i8_zext_i16(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV32-NEXT:  [[ENTRY:.*:]]
; RV32-NEXT:    br label %[[VECTOR_PH:.*]]
; RV32:       [[VECTOR_PH]]:
; RV32-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x ptr> poison, ptr [[OUT]], i64 0
; RV32-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x ptr> [[BROADCAST_SPLATINSERT]], <vscale x 8 x ptr> poison, <vscale x 8 x i32> zeroinitializer
; RV32-NEXT:    br label %[[VECTOR_BODY:.*]]
; RV32:       [[VECTOR_BODY]]:
; RV32-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[AVL:%.*]] = phi i32 [ 16, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; RV32-NEXT:    [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true)
; RV32-NEXT:    [[TMP1:%.*]] = shl i32 [[INDEX]], 12
; RV32-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i32 [[TMP1]]
; RV32-NEXT:    [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr align 1 [[TMP2]], i32 4096, <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    call void @llvm.vp.scatter.nxv8i8.nxv8p0(<vscale x 8 x i8> [[TMP3]], <vscale x 8 x ptr> align 1 [[BROADCAST_SPLAT]], <vscale x 8 x i1> splat (i1 true), i32 [[TMP0]])
; RV32-NEXT:    [[CURRENT_ITERATION_NEXT]] = add nuw i32 [[TMP0]], [[INDEX]]
; RV32-NEXT:    [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP0]]
; RV32-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0
; RV32-NEXT:    br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; RV32:       [[MIDDLE_BLOCK]]:
; RV32-NEXT:    br label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %i = phi i8 [ 0, %entry ], [ %i.next, %loop ]
  %idx = zext i8 %i to i16
  %ptr = getelementptr [1024 x i8], ptr %arr, i16 %idx
  %val = load i8, ptr %ptr, align 1
  store i8 %val, ptr %out, align 1
  %i.next = add i8 %i, 4
  %cmp = icmp ult i8 %i.next, 64
  br i1 %cmp, label %loop, label %exit

exit:
  ret void
}

; Negative test
define void @narrow_iv_i8_sext_i64_wrapping(ptr noalias %arr, ptr noalias %out) {
; RV64-LABEL: define void @narrow_iv_i8_sext_i64_wrapping(
; RV64-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV64-NEXT:  [[ENTRY:.*]]:
; RV64-NEXT:    br label %[[LOOP:.*]]
; RV64:       [[LOOP]]:
; RV64-NEXT:    [[I:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
; RV64-NEXT:    [[IDX:%.*]] = sext i8 [[I]] to i64
; RV64-NEXT:    [[PTR:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], i64 [[IDX]]
; RV64-NEXT:    [[VAL:%.*]] = load i8, ptr [[PTR]], align 1
; RV64-NEXT:    store i8 [[VAL]], ptr [[OUT]], align 1
; RV64-NEXT:    [[I_NEXT]] = add i8 [[I]], 4
; RV64-NEXT:    [[CMP:%.*]] = icmp ne i8 [[I_NEXT]], 0
; RV64-NEXT:    br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
; RV64:       [[EXIT]]:
; RV64-NEXT:    ret void
;
; RV32-LABEL: define void @narrow_iv_i8_sext_i64_wrapping(
; RV32-SAME: ptr noalias [[ARR:%.*]], ptr noalias [[OUT:%.*]]) #[[ATTR0]] {
; RV32-NEXT:  [[ENTRY:.*]]:
; RV32-NEXT:    br label %[[LOOP:.*]]
; RV32:       [[LOOP]]:
; RV32-NEXT:    [[I:%.*]] = phi i8 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
; RV32-NEXT:    [[IDX:%.*]] = sext i8 [[I]] to i64
; RV32-NEXT:    [[PTR:%.*]] = getelementptr [1024 x i8], ptr [[ARR]], i64 [[IDX]]
; RV32-NEXT:    [[VAL:%.*]] = load i8, ptr [[PTR]], align 1
; RV32-NEXT:    store i8 [[VAL]], ptr [[OUT]], align 1
; RV32-NEXT:    [[I_NEXT]] = add i8 [[I]], 4
; RV32-NEXT:    [[CMP:%.*]] = icmp ne i8 [[I_NEXT]], 0
; RV32-NEXT:    br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]]
; RV32:       [[EXIT]]:
; RV32-NEXT:    ret void
;
entry:
  br label %loop

loop:
  %i = phi i8 [ 0, %entry ], [ %i.next, %loop ]
  %idx = sext i8 %i to i64
  %ptr = getelementptr [1024 x i8], ptr %arr, i64 %idx
  %val = load i8, ptr %ptr, align 1
  store i8 %val, ptr %out, align 1
  %i.next = add i8 %i, 4
  %cmp = icmp ne i8 %i.next, 0
  br i1 %cmp, label %loop, label %exit

exit:
  ret void
}