| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5 |
| ; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v -S < %s | FileCheck %s |
| ; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v -vectorizer-consider-reg-pressure=true -S < %s | FileCheck %s |
| ; RUN: opt -p loop-vectorize -mtriple riscv64 -mattr=+v -vectorizer-consider-reg-pressure=false -S < %s | FileCheck %s --check-prefix=NO-REG-PRESSURE-CHECK |
| |
| define void @f(ptr noalias %p0, ptr noalias %p1, ptr noalias %p2) { |
| ; CHECK-LABEL: define void @f( |
| ; CHECK-SAME: ptr noalias [[P0:%.*]], ptr noalias [[P1:%.*]], ptr noalias [[P2:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P0]], i64 -1 |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[TMP7:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 16, i1 true) |
| ; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 1 |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP8]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP2]], i64 2, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP7]], 3 |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP4]] |
| ; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP5]], i64 3, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[TMP7]], 2 |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP11]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP12]], i64 4, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP7]], 3 |
| ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[P1]], i64 [[TMP19]] |
| ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[TMP20]], i8 0 |
| ; CHECK-NEXT: [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP6]], 3 |
| ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call <vscale x 48 x i8> @llvm.vector.interleave3.nxv48i8(<vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP9]]) |
| ; CHECK-NEXT: call void @llvm.vp.store.nxv48i8.p0(<vscale x 48 x i8> [[INTERLEAVED_VEC]], ptr align 1 [[TMP21]], <vscale x 48 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]]) |
| ; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP6]] to i64 |
| ; CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP13]], [[TMP7]] |
| ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]] |
| ; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; CHECK-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: br label %[[EXIT:.*]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: ret void |
| ; |
| ; NO-REG-PRESSURE-CHECK-LABEL: define void @f( |
| ; NO-REG-PRESSURE-CHECK-SAME: ptr noalias [[P0:%.*]], ptr noalias [[P1:%.*]], ptr noalias [[P2:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[ENTRY:.*:]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: br label %[[VECTOR_PH:.*]] |
| ; NO-REG-PRESSURE-CHECK: [[VECTOR_PH]]: |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P0]], i64 -1 |
| ; NO-REG-PRESSURE-CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; NO-REG-PRESSURE-CHECK: [[VECTOR_BODY]]: |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP7:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[CURRENT_ITERATION_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[AVL:%.*]] = phi i64 [ 1025, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 16, i1 true) |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 1 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP8]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP2]], i64 2, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP7]], 3 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP4]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP5]], i64 3, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[TMP7]], 2 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP11]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP9:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vp.strided.load.nxv16i8.p0.i64(ptr align 1 [[TMP12]], i64 4, <vscale x 16 x i1> splat (i1 true), i32 [[TMP6]]) |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP7]], 3 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[P1]], i64 [[TMP19]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[TMP20]], i8 0 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[INTERLEAVE_EVL:%.*]] = mul nuw nsw i32 [[TMP6]], 3 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call <vscale x 48 x i8> @llvm.vector.interleave3.nxv48i8(<vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP10]], <vscale x 16 x i8> [[TMP9]]) |
| ; NO-REG-PRESSURE-CHECK-NEXT: call void @llvm.vp.store.nxv48i8.p0(<vscale x 48 x i8> [[INTERLEAVED_VEC]], ptr align 1 [[TMP21]], <vscale x 48 x i1> splat (i1 true), i32 [[INTERLEAVE_EVL]]) |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP6]] to i64 |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[CURRENT_ITERATION_NEXT]] = add nuw i64 [[TMP13]], [[TMP7]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP13]] |
| ; NO-REG-PRESSURE-CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 |
| ; NO-REG-PRESSURE-CHECK-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; NO-REG-PRESSURE-CHECK: [[MIDDLE_BLOCK]]: |
| ; NO-REG-PRESSURE-CHECK-NEXT: br label %[[EXIT:.*]] |
| ; NO-REG-PRESSURE-CHECK: [[EXIT]]: |
| ; NO-REG-PRESSURE-CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %wide.iv.0 = phi i64 [ 0, %entry ], [ %wide.iv.0.next, %loop ] |
| %wide.iv.1 = phi i64 [ 0, %entry ], [ %wide.iv.1.next, %loop ] |
| %wide.iv.2 = phi i64 [ 0, %entry ], [ %wide.iv.2.next, %loop ] |
| |
| %wide.iv.0.sub = sub i64 %wide.iv.0, 1 |
| %a.gep0 = getelementptr i8, ptr %p0, i64 %wide.iv.0.sub |
| %a = load i8, ptr %a.gep0 |
| |
| %wide.iv.1.sub = sub i64 %wide.iv.1, 1 |
| %b.gep0 = getelementptr i8, ptr %p0, i64 %wide.iv.1.sub |
| %b = load i8, ptr %b.gep0 |
| |
| %wide.iv.2.sub = sub i64 %wide.iv.2, 1 |
| %c.gep0 = getelementptr i8, ptr %p0, i64 %wide.iv.2.sub |
| %c = load i8, ptr %c.gep0 |
| |
| %iv.mul = mul i64 %iv, 3 |
| %base = getelementptr i8, ptr %p1, i64 %iv.mul |
| |
| %a.gep1 = getelementptr i8, ptr %base, i8 0 |
| store i8 %a, ptr %a.gep1 |
| |
| %b.gep1 = getelementptr i8, ptr %base, i8 1 |
| store i8 %b, ptr %b.gep1 |
| |
| %c.gep1 = getelementptr i8, ptr %base, i8 2 |
| store i8 %c, ptr %c.gep1 |
| |
| %iv.next = add i64 %iv, 1 |
| %wide.iv.0.next = add i64 %wide.iv.0, 2 |
| %wide.iv.1.next = add i64 %wide.iv.1, 3 |
| %wide.iv.2.next = add i64 %wide.iv.2, 4 |
| %done = icmp eq i64 %iv, 1024 |
| br i1 %done, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
