blob: f535665475838035152f37415f4a22930124e1c5 [file]
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name VAL_ --version 6
; RUN: opt < %s -passes=loop-interchange -cache-line-size=64 -da-enable-dependence-test=all -S | FileCheck %s
@A10 = local_unnamed_addr global [3 x [3 x i32]] zeroinitializer, align 16
;; Test to make sure we can handle zext instructions introduced by
;; IndVarSimplify.
;;
;; for (int i = 0; i < 2; ++i)
;; for(int j = 0; j < n; ++j) {
;; A[j][i] = i;
;; }
@A11 = local_unnamed_addr global [3 x [3 x i32]] zeroinitializer, align 16
define void @interchange_11(i32 %n) {
; CHECK-LABEL: define void @interchange_11(
; CHECK-SAME: i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br label %[[FOR_BODY4_PREHEADER:.*]]
; CHECK: [[FOR_COND1_PREHEADER_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER:.*]]
; CHECK: [[FOR_COND_LOOPEXIT:.*]]:
; CHECK-NEXT: [[EXITCOND28:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT27:%.*]], 2
; CHECK-NEXT: br i1 [[EXITCOND28]], label %[[FOR_COND1_PREHEADER]], label %[[FOR_BODY4_SPLIT:.*]]
; CHECK: [[FOR_COND1_PREHEADER]]:
; CHECK-NEXT: [[INDVARS_IV26:%.*]] = phi i64 [ [[INDVARS_IV_NEXT27]], %[[FOR_COND_LOOPEXIT]] ], [ 0, %[[FOR_COND1_PREHEADER_PREHEADER]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT27]] = add nuw nsw i64 [[INDVARS_IV26]], 1
; CHECK-NEXT: br label %[[FOR_BODY4_SPLIT1:.*]]
; CHECK: [[FOR_BODY4_PREHEADER]]:
; CHECK-NEXT: br label %[[FOR_BODY4:.*]]
; CHECK: [[FOR_COND_CLEANUP:.*]]:
; CHECK-NEXT: ret void
; CHECK: [[FOR_BODY4]]:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP3:%.*]], %[[FOR_BODY4_SPLIT]] ], [ 0, %[[FOR_BODY4_PREHEADER]] ]
; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER_PREHEADER]]
; CHECK: [[FOR_BODY4_SPLIT1]]:
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [3 x [3 x i32]], ptr @A10, i64 0, i64 [[INDVARS_IV]], i64 [[INDVARS_IV_NEXT27]]
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX10]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[N_WIDE:%.*]] = zext i32 [[N]] to i64
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[N_WIDE]]
; CHECK-NEXT: br label %[[FOR_COND_LOOPEXIT]]
; CHECK: [[FOR_BODY4_SPLIT]]:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
; CHECK-NEXT: [[TMP3]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP3]], [[TMP0]]
; CHECK-NEXT: br i1 [[TMP2]], label %[[FOR_BODY4]], label %[[FOR_COND_CLEANUP]]
;
entry:
br label %for.cond1.preheader
for.cond.loopexit: ; preds = %for.body4
%exitcond28 = icmp ne i64 %indvars.iv.next27, 2
br i1 %exitcond28, label %for.cond1.preheader, label %for.cond.cleanup
for.cond1.preheader: ; preds = %for.cond.loopexit, %entry
%indvars.iv26 = phi i64 [ 0, %entry ], [ %indvars.iv.next27, %for.cond.loopexit ]
%indvars.iv.next27 = add nuw nsw i64 %indvars.iv26, 1
br label %for.body4
for.cond.cleanup: ; preds = %for.cond.loopexit
ret void
for.body4: ; preds = %for.body4, %for.cond1.preheader
%indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body4 ]
; The store below does not appear in the C snippet above.
; With two stores in the loop there may be WAW dependences, and interchange is illegal.
; %arrayidx6 = getelementptr inbounds [3 x [3 x i32]], [3 x [3 x i32]]* @A10, i64 0, i64 %indvars.iv, i64 %indvars.iv26
; %tmp = trunc i64 %indvars.iv26 to i32
; store i32 %tmp, i32* %arrayidx6, align 4
%arrayidx10 = getelementptr inbounds [3 x [3 x i32]], ptr @A10, i64 0, i64 %indvars.iv, i64 %indvars.iv.next27
%tmp1 = trunc i64 %indvars.iv to i32
store i32 %tmp1, ptr %arrayidx10, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%n.wide = zext i32 %n to i64
%exitcond = icmp ne i64 %indvars.iv.next, %n.wide
br i1 %exitcond, label %for.body4, label %for.cond.loopexit
}