llvm/test/CodeGen/PowerPC/bswap64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN:   -mcpu=pwr8 | FileCheck %s --check-prefix=POWER-8
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN:   -mcpu=pwr8 -mattr=-altivec | FileCheck %s --check-prefix=POWER-8-NO-ALTIVEC
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN:   -mcpu=pwr9 | FileCheck %s --check-prefix=POWER-9
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
; RUN:   -mcpu=pwr9 -vec-extabi | FileCheck %s --check-prefix=POWER-9
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN:   -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=POWER-9-NO-ALTIVEC
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \
; RUN:   -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=POWER-9-NO-ALTIVEC

declare i64 @llvm.bswap.i64(i64)

; This patch verifies that the compiler generates optimized assembly for Power 8 64-bit
; byte swap operations that enables instruction-level parallelism.
define i64 @bswap64(i64 %x) {
; POWER-8-LABEL: bswap64:
; POWER-8:       # %bb.0: # %entry
; POWER-8-NEXT:    rotlwi 4, 3, 8
; POWER-8-NEXT:    rldicl 5, 3, 32, 32
; POWER-8-NEXT:    rlwimi 4, 3, 24, 0, 7
; POWER-8-NEXT:    rlwimi 4, 3, 24, 16, 23
; POWER-8-NEXT:    rotlwi 3, 5, 8
; POWER-8-NEXT:    rlwimi 3, 5, 24, 0, 7
; POWER-8-NEXT:    rlwimi 3, 5, 24, 16, 23
; POWER-8-NEXT:    rldimi 3, 4, 32, 0
; POWER-8-NEXT:    blr
;
; POWER-8-NO-ALTIVEC-LABEL: bswap64:
; POWER-8-NO-ALTIVEC:       # %bb.0: # %entry
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 5, 3, 16
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 4, 3, 8
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 5, 8, 48
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 5, 3, 24
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 5, 16, 40
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 5, 3, 32
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 5, 24, 32
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 5, 3, 48
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 5, 40, 16
; POWER-8-NO-ALTIVEC-NEXT:    rotldi 5, 3, 56
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 5, 48, 8
; POWER-8-NO-ALTIVEC-NEXT:    rldimi 4, 3, 56, 0
; POWER-8-NO-ALTIVEC-NEXT:    mr 3, 4
; POWER-8-NO-ALTIVEC-NEXT:    blr
;
; POWER-9-LABEL: bswap64:
; POWER-9:       # %bb.0: # %entry
; POWER-9-NEXT:    mtvsrdd 34, 3, 3
; POWER-9-NEXT:    xxbrd 0, 34
; POWER-9-NEXT:    mffprd 3, 0
; POWER-9-NEXT:    blr
;
; POWER-9-NO-ALTIVEC-LABEL: bswap64:
; POWER-9-NO-ALTIVEC:       # %bb.0: # %entry
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 5, 3, 16
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 4, 3, 8
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 5, 8, 48
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 5, 3, 24
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 5, 16, 40
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 5, 3, 32
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 5, 24, 32
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 5, 3, 48
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 5, 40, 16
; POWER-9-NO-ALTIVEC-NEXT:    rotldi 5, 3, 56
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 5, 48, 8
; POWER-9-NO-ALTIVEC-NEXT:    rldimi 4, 3, 56, 0
; POWER-9-NO-ALTIVEC-NEXT:    mr 3, 4
; POWER-9-NO-ALTIVEC-NEXT:    blr
entry:
  %0 = call i64 @llvm.bswap.i64(i64 %x)
  ret i64 %0
}