llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu8.03 -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s

declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)

define amdgpu_kernel void @frexp_exp_f16(
; VI-SDAG-LABEL: frexp_exp_f16:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
; VI-SDAG-NEXT:    s_mov_b32 s6, -1
; VI-SDAG-NEXT:    s_mov_b32 s10, s6
; VI-SDAG-NEXT:    s_mov_b32 s11, s7
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    s_mov_b32 s8, s2
; VI-SDAG-NEXT:    s_mov_b32 s9, s3
; VI-SDAG-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
; VI-SDAG-NEXT:    s_mov_b32 s4, s0
; VI-SDAG-NEXT:    s_mov_b32 s5, s1
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0)
; VI-SDAG-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
; VI-SDAG-NEXT:    buffer_store_short v0, off, s[4:7], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: frexp_exp_f16:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s6, -1
; VI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    s_mov_b64 s[4:5], s[2:3]
; VI-GISEL-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    v_frexp_exp_i16_f16_e32 v0, s2
; VI-GISEL-NEXT:    s_mov_b64 s[2:3], s[6:7]
; VI-GISEL-NEXT:    s_nop 2
; VI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
    ptr addrspace(1) %r,
    ptr addrspace(1) %a) {
entry:
  %a.val = load half, ptr addrspace(1) %a
  %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
  store i16 %r.val, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @frexp_exp_f16_sext(
; VI-SDAG-LABEL: frexp_exp_f16_sext:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
; VI-SDAG-NEXT:    s_mov_b32 s6, -1
; VI-SDAG-NEXT:    s_mov_b32 s10, s6
; VI-SDAG-NEXT:    s_mov_b32 s11, s7
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    s_mov_b32 s8, s2
; VI-SDAG-NEXT:    s_mov_b32 s9, s3
; VI-SDAG-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
; VI-SDAG-NEXT:    s_mov_b32 s4, s0
; VI-SDAG-NEXT:    s_mov_b32 s5, s1
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0)
; VI-SDAG-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
; VI-SDAG-NEXT:    v_bfe_i32 v0, v0, 0, 16
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: frexp_exp_f16_sext:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s6, -1
; VI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    s_mov_b64 s[4:5], s[2:3]
; VI-GISEL-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    v_frexp_exp_i16_f16_e32 v0, s2
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    s_sext_i32_i16 s2, s2
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT:    s_mov_b64 s[2:3], s[6:7]
; VI-GISEL-NEXT:    s_nop 1
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
    ptr addrspace(1) %r,
    ptr addrspace(1) %a) {
entry:
  %a.val = load half, ptr addrspace(1) %a
  %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
  %r.val.sext = sext i16 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @frexp_exp_f16_zext(
; VI-SDAG-LABEL: frexp_exp_f16_zext:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-SDAG-NEXT:    s_mov_b32 s7, 0xf000
; VI-SDAG-NEXT:    s_mov_b32 s6, -1
; VI-SDAG-NEXT:    s_mov_b32 s10, s6
; VI-SDAG-NEXT:    s_mov_b32 s11, s7
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    s_mov_b32 s8, s2
; VI-SDAG-NEXT:    s_mov_b32 s9, s3
; VI-SDAG-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
; VI-SDAG-NEXT:    s_mov_b32 s4, s0
; VI-SDAG-NEXT:    s_mov_b32 s5, s1
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0)
; VI-SDAG-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: frexp_exp_f16_zext:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT:    s_mov_b32 s6, -1
; VI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    s_mov_b64 s[4:5], s[2:3]
; VI-GISEL-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    v_frexp_exp_i16_f16_e32 v0, s2
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    s_and_b32 s2, 0xffff, s2
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT:    s_mov_b64 s[2:3], s[6:7]
; VI-GISEL-NEXT:    s_nop 1
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
    ptr addrspace(1) %r,
    ptr addrspace(1) %a) {
entry:
  %a.val = load half, ptr addrspace(1) %a
  %r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
  %r.val.zext = zext i16 %r.val to i32
  store i32 %r.val.zext, ptr addrspace(1) %r
  ret void
}

define amdgpu_ps i32 @v_test_frexp_exp_f16(half %src) {
; VI-SDAG-LABEL: v_test_frexp_exp_f16:
; VI-SDAG:       ; %bb.0:
; VI-SDAG-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
; VI-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
; VI-SDAG-NEXT:    ; return to shader part epilog
;
; VI-GISEL-LABEL: v_test_frexp_exp_f16:
; VI-GISEL:       ; %bb.0:
; VI-GISEL-NEXT:    v_frexp_exp_i16_f16_e32 v0, v0
; VI-GISEL-NEXT:    v_readfirstlane_b32 s0, v0
; VI-GISEL-NEXT:    ; return to shader part epilog
  %frexp.exp = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %src)
  %frexp.exp.zext = zext i16 %frexp.exp to i32
  ret i32 %frexp.exp.zext
}