llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu11.70 < %s | FileCheck -check-prefixes=GCN,GFX1170 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu11.70 < %s | FileCheck -check-prefixes=GCN,GFX1170 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GCN,GFX12 %s

define float @test_amdgcn_dot4_f32_fp8_bf8(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_bf8_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_bf8_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fabs_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %fabs.fneg.c = call float @llvm.fabs.f32(float %fneg.c)
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %fabs.fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_bf8_fneg_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %fneg.fabs.c = fneg float %fabs.c
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %fneg.fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_fp8(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_fp8_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_fp8_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fabs_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %fabs.fneg.c = call float @llvm.fabs.f32(float %fneg.c)
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %fabs.fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_fp8_fneg_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %fneg.fabs.c = fneg float %fabs.c
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %fneg.fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_fp8(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_fp8_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_fp8_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fabs_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %fabs.fneg.c = call float @llvm.fabs.f32(float %fneg.c)
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %fabs.fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_fp8_fp8_fneg_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_fp8_fp8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %fneg.fabs.c = fneg float %fabs.c
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %fneg.fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_bf8(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_bf8_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %fabs.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_bf8_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fabs_fneg:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fneg.c = fneg float %c
  %fabs.fneg.c = call float @llvm.fabs.f32(float %fneg.c)
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %fabs.fneg.c)
  ret float %ret
}

define float @test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs(i32 %a, i32 %b, float %c) {
; GFX1170-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs:
; GFX1170:       ; %bb.0: ; %entry
; GFX1170-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1170-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX1170-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_amdgcn_dot4_f32_bf8_bf8_fneg_fabs:
; GFX12:       ; %bb.0: ; %entry
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dot4_f32_bf8_bf8 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
entry:
  %fabs.c = call float @llvm.fabs.f32(float %c)
  %fneg.fabs.c = fneg float %fabs.c
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %fneg.fabs.c)
  ret float %ret
}

define amdgpu_ps float @test_amdgcn_dot4_f32_fp8_bf8_s_s_s(i32 inreg %a, i32 inreg %b, float inreg %c) {
; GCN-LABEL: test_amdgcn_dot4_f32_fp8_bf8_s_s_s:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_mov_b32_e32 v0, s2
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT:    v_dot4_f32_fp8_bf8 v0, s0, s1, v0
; GCN-NEXT:    ; return to shader part epilog
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define amdgpu_ps float @test_amdgcn_dot4_f32_bf8_fp8_s_s_s(i32 inreg %a, i32 inreg %b, float inreg %c) {
; GCN-LABEL: test_amdgcn_dot4_f32_bf8_fp8_s_s_s:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_mov_b32_e32 v0, s2
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT:    v_dot4_f32_bf8_fp8 v0, s0, s1, v0
; GCN-NEXT:    ; return to shader part epilog
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define amdgpu_ps float @test_amdgcn_dot4_f32_fp8_fp8_s_s_s(i32 inreg %a, i32 inreg %b, float inreg %c) {
; GCN-LABEL: test_amdgcn_dot4_f32_fp8_fp8_s_s_s:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_mov_b32_e32 v0, s2
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT:    v_dot4_f32_fp8_fp8 v0, s0, s1, v0
; GCN-NEXT:    ; return to shader part epilog
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %c)
  ret float %ret
}

define amdgpu_ps float @test_amdgcn_dot4_f32_bf8_bf8_s_s_s(i32 inreg %a, i32 inreg %b, float inreg %c) {
; GCN-LABEL: test_amdgcn_dot4_f32_bf8_bf8_s_s_s:
; GCN:       ; %bb.0: ; %entry
; GCN-NEXT:    v_mov_b32_e32 v0, s2
; GCN-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GCN-NEXT:    v_dot4_f32_bf8_bf8 v0, s0, s1, v0
; GCN-NEXT:    ; return to shader part epilog
entry:
  %ret = call float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %c)
  ret float %ret
}

declare float @llvm.amdgcn.dot4.f32.fp8.bf8(i32 %a, i32 %b, float %c)
declare float @llvm.amdgcn.dot4.f32.bf8.fp8(i32 %a, i32 %b, float %c)
declare float @llvm.amdgcn.dot4.f32.fp8.fp8(i32 %a, i32 %b, float %c)
declare float @llvm.amdgcn.dot4.f32.bf8.bf8(i32 %a, i32 %b, float %c)

declare float @llvm.fabs.f32(float %a)