llvm/test/CodeGen/AMDGPU/fold-commute-sgpr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgpu12.00-amd-amdhsa -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s

---
name: fold_commute_sgprs
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: fold_commute_sgprs
    ; CHECK: liveins: $sgpr0, $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; CHECK-NEXT: [[V_ADD_NC_U16_fake16_e64_dpp:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64_dpp [[COPY1]], 0, [[COPY2]], 0, [[COPY3]], 0, 0, 280, 15, 15, 1, implicit $exec
    %0:sreg_32 = COPY $sgpr0
    %1:sreg_32 = IMPLICIT_DEF
    %2:vgpr_32 = COPY %1:sreg_32
    %3:vgpr_32 = COPY %0:sreg_32
    %4:sreg_32 = COPY $sgpr1
    %5:vgpr_32 = V_ADD_NC_U16_fake16_e64_dpp %2:vgpr_32, 0, %3:vgpr_32, 0, %4:sreg_32, 0, 0, 280, 15, 15, 1, implicit $exec
...