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llvm/llvm-project/e14b11b74dcafea1e2a71b9788b85b34ab4cf1e6/./llvm/test/CodeGen/AMDGPU/fceil64.ll
blob: 1c03167b42b9c39ce77b97fd56f5aa748a97a629 [file]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgpu7.04 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
declare double @llvm.ceil.f64(double) nounwind readnone
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
define amdgpu_kernel void @fceil_f64(ptr addrspace(1) %out, double %x) {
; SI-LABEL: fceil_f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s5, 0xfffff
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s8, s3, 0xb0014
; SI-NEXT: s_addk_i32 s8, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], s8
; SI-NEXT: s_andn2_b64 s[4:5], s[2:3], s[4:5]
; SI-NEXT: s_and_b32 s9, s3, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: s_cselect_b32 s9, s3, s5
; SI-NEXT: s_cselect_b32 s8, s2, s4
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[2:3], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], 0
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_and_b64 s[2:3], s[2:3], vcc
; SI-NEXT: s_and_b64 s[2:3], s[2:3], exec
; SI-NEXT: s_cselect_b32 s0, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
%y = call double @llvm.ceil.f64(double %x) nounwind readnone
store double %y, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fceil_v2f64(ptr addrspace(1) %out, <2 x double> %x) {
; SI-LABEL: fceil_v2f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s7, 0xfffff
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s12, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; SI-NEXT: s_and_b32 s3, s11, 0x80000000
; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s12, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s12, 51
; SI-NEXT: s_cselect_b32 s13, s11, s1
; SI-NEXT: s_cselect_b32 s12, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_mov_b32_e32 v1, s13
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[10:11], 0
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[8:9], s[4:5]
; SI-NEXT: s_and_b32 s6, s9, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s6, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v2, s4
; SI-NEXT: v_mov_b32_e32 v3, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[2:3]
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[8:9], 0
; SI-NEXT: v_mov_b32_e32 v0, 0
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[2:3], s[12:13], v[0:1]
; SI-NEXT: v_mov_b32_e32 v1, s3
; SI-NEXT: v_add_f64 v[0:1], s[4:5], v[0:1]
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
store <2 x double> %y, ptr addrspace(1) %out
ret void
}
; FIXME-FUNC-LABEL: {{^}}fceil_v3f64:
; FIXME-CI: v_ceil_f64_e32
; FIXME-CI: v_ceil_f64_e32
; FIXME-CI: v_ceil_f64_e32
; define amdgpu_kernel void @fceil_v3f64(ptr addrspace(1) %out, <3 x double> %x) {
; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
; store <3 x double> %y, ptr addrspace(1) %out
; ret void
; }
define amdgpu_kernel void @fceil_v4f64(ptr addrspace(1) %out, <4 x double> %x) {
; SI-LABEL: fceil_v4f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x11
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s7, 0xfffff
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: v_mov_b32_e32 v4, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s16, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[6:7], s16
; SI-NEXT: s_and_b32 s3, s11, 0x80000000
; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s16, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s16, 51
; SI-NEXT: s_cselect_b32 s17, s11, s1
; SI-NEXT: s_cselect_b32 s16, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_mov_b32_e32 v1, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[10:11], 0
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v5, s3
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[8:9], s[4:5]
; SI-NEXT: s_and_b32 s10, s9, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[8:9], 0
; SI-NEXT: v_add_f64 v[2:3], s[16:17], v[4:5]
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v5, s3
; SI-NEXT: s_bfe_u32 s3, s15, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[8:9], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[8:9]
; SI-NEXT: s_and_b32 s10, s15, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s9, s15, s9
; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[14:15], 0
; SI-NEXT: v_add_f64 v[0:1], s[4:5], v[4:5]
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v5, s3
; SI-NEXT: s_bfe_u32 s3, s13, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[12:13], s[4:5]
; SI-NEXT: s_and_b32 s6, s13, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s6, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s13, s5
; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: v_mov_b32_e32 v7, s5
; SI-NEXT: v_mov_b32_e32 v6, s4
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[6:7]
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[12:13], 0
; SI-NEXT: v_add_f64 v[6:7], s[8:9], v[4:5]
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v5, s3
; SI-NEXT: v_add_f64 v[4:5], s[4:5], v[4:5]
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
store <4 x double> %y, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fceil_v8f64(ptr addrspace(1) %out, <8 x double> %x) {
; SI-LABEL: fceil_v8f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x19
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s7, 0xfffff
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: v_mov_b32_e32 v8, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
; SI-NEXT: s_add_i32 s24, s0, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[0:1], s[6:7], s24
; SI-NEXT: s_and_b32 s3, s11, 0x80000000
; SI-NEXT: s_andn2_b64 s[0:1], s[10:11], s[0:1]
; SI-NEXT: s_cmp_lt_i32 s24, 0
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cselect_b32 s1, s3, s1
; SI-NEXT: s_cmp_gt_i32 s24, 51
; SI-NEXT: s_cselect_b32 s25, s11, s1
; SI-NEXT: s_cselect_b32 s24, s10, s0
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_mov_b32_e32 v1, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[10:11], 0
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s9, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[8:9], s[4:5]
; SI-NEXT: s_and_b32 s10, s9, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s9, s5
; SI-NEXT: s_cselect_b32 s4, s8, s4
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[8:9], 0
; SI-NEXT: v_add_f64 v[2:3], s[24:25], v[8:9]
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s15, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[8:9], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[8:9]
; SI-NEXT: s_and_b32 s10, s15, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s9, s15, s9
; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[14:15], 0
; SI-NEXT: v_add_f64 v[0:1], s[4:5], v[8:9]
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s13, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[12:13], s[4:5]
; SI-NEXT: s_and_b32 s10, s13, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s13, s5
; SI-NEXT: s_cselect_b32 s4, s12, s4
; SI-NEXT: v_mov_b32_e32 v4, s4
; SI-NEXT: v_mov_b32_e32 v5, s5
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[4:5]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[12:13], 0
; SI-NEXT: v_add_f64 v[6:7], s[8:9], v[8:9]
; SI-NEXT: s_and_b64 s[8:9], s[10:11], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s19, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[8:9], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[8:9], s[18:19], s[8:9]
; SI-NEXT: s_and_b32 s10, s19, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s9, s19, s9
; SI-NEXT: s_cselect_b32 s8, s18, s8
; SI-NEXT: v_mov_b32_e32 v4, s8
; SI-NEXT: v_mov_b32_e32 v5, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[4:5]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[18:19], 0
; SI-NEXT: v_add_f64 v[4:5], s[4:5], v[8:9]
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s17, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[16:17], s[4:5]
; SI-NEXT: s_and_b32 s10, s17, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s10, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s17, s5
; SI-NEXT: s_cselect_b32 s4, s16, s4
; SI-NEXT: v_mov_b32_e32 v11, s5
; SI-NEXT: v_mov_b32_e32 v10, s4
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[10:11]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[16:17], 0
; SI-NEXT: v_add_f64 v[12:13], s[8:9], v[8:9]
; SI-NEXT: s_and_b64 s[8:9], s[10:11], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s23, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[8:9], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[8:9], s[22:23], s[8:9]
; SI-NEXT: s_and_b32 s10, s23, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s10, s9
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s9, s23, s9
; SI-NEXT: s_cselect_b32 s8, s22, s8
; SI-NEXT: v_mov_b32_e32 v11, s9
; SI-NEXT: v_mov_b32_e32 v10, s8
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[10:11]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[22:23], 0
; SI-NEXT: v_add_f64 v[10:11], s[4:5], v[8:9]
; SI-NEXT: s_and_b64 s[4:5], s[10:11], vcc
; SI-NEXT: s_and_b64 s[4:5], s[4:5], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: s_bfe_u32 s3, s21, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], s3
; SI-NEXT: s_andn2_b64 s[4:5], s[20:21], s[4:5]
; SI-NEXT: s_and_b32 s6, s21, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s4, 0, s4
; SI-NEXT: s_cselect_b32 s5, s6, s5
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s5, s21, s5
; SI-NEXT: s_cselect_b32 s4, s20, s4
; SI-NEXT: v_mov_b32_e32 v15, s5
; SI-NEXT: v_mov_b32_e32 v14, s4
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[14:15]
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[20:21], 0
; SI-NEXT: v_add_f64 v[16:17], s[8:9], v[8:9]
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_mov_b32_e32 v9, s3
; SI-NEXT: v_add_f64 v[14:15], s[4:5], v[8:9]
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:48
; SI-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:32
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
store <8 x double> %y, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @fceil_v16f64(ptr addrspace(1) %out, <16 x double> %x) {
; SI-LABEL: fceil_v16f64:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x29
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s1, 0xfffff
; SI-NEXT: s_mov_b32 s0, s2
; SI-NEXT: v_mov_b32_e32 v16, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s3, s11, 0xb0014
; SI-NEXT: s_addk_i32 s3, 0xfc01
; SI-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
; SI-NEXT: s_and_b32 s24, s11, 0x80000000
; SI-NEXT: s_andn2_b64 s[6:7], s[10:11], s[6:7]
; SI-NEXT: s_cmp_lt_i32 s3, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s24, s7
; SI-NEXT: s_cmp_gt_i32 s3, 51
; SI-NEXT: s_cselect_b32 s27, s11, s7
; SI-NEXT: s_cselect_b32 s26, s10, s6
; SI-NEXT: v_mov_b32_e32 v0, s26
; SI-NEXT: v_mov_b32_e32 v1, s27
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[10:11], 0
; SI-NEXT: v_cmp_gt_f64_e64 s[36:37], s[20:21], 0
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s9, 0xb0014
; SI-NEXT: s_add_i32 s10, s6, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[0:1], s10
; SI-NEXT: s_andn2_b64 s[6:7], s[8:9], s[6:7]
; SI-NEXT: s_and_b32 s11, s9, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s10, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s11, s7
; SI-NEXT: s_cmp_gt_i32 s10, 51
; SI-NEXT: s_cselect_b32 s7, s9, s7
; SI-NEXT: s_cselect_b32 s6, s8, s6
; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: v_mov_b32_e32 v1, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[8:9], 0
; SI-NEXT: v_mov_b32_e32 v17, s3
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s10, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s8, s15, 0xb0014
; SI-NEXT: s_add_i32 s11, s8, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[8:9], s[0:1], s11
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[8:9]
; SI-NEXT: s_and_b32 s24, s15, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s11, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s24, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
; SI-NEXT: s_cselect_b32 s25, s15, s9
; SI-NEXT: s_cselect_b32 s24, s14, s8
; SI-NEXT: v_mov_b32_e32 v0, s24
; SI-NEXT: v_mov_b32_e32 v1, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[14:15], 0
; SI-NEXT: v_add_f64 v[2:3], s[26:27], v[16:17]
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s8, s13, 0xb0014
; SI-NEXT: s_add_i32 s11, s8, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[8:9], s[0:1], s11
; SI-NEXT: s_andn2_b64 s[8:9], s[12:13], s[8:9]
; SI-NEXT: s_and_b32 s14, s13, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s11, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s14, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
; SI-NEXT: s_cselect_b32 s35, s13, s9
; SI-NEXT: s_cselect_b32 s34, s12, s8
; SI-NEXT: v_mov_b32_e32 v0, s34
; SI-NEXT: v_mov_b32_e32 v1, s35
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[12:13], 0
; SI-NEXT: v_mov_b32_e32 v17, s10
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s33, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s8, s19, 0xb0014
; SI-NEXT: s_add_i32 s11, s8, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[8:9], s[0:1], s11
; SI-NEXT: s_andn2_b64 s[8:9], s[18:19], s[8:9]
; SI-NEXT: s_and_b32 s12, s19, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s11, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s12, s9
; SI-NEXT: s_cmp_gt_i32 s11, 51
; SI-NEXT: s_cselect_b32 s31, s19, s9
; SI-NEXT: s_cselect_b32 s30, s18, s8
; SI-NEXT: v_mov_b32_e32 v0, s30
; SI-NEXT: v_mov_b32_e32 v1, s31
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[18:19], 0
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s38, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s8, s17, 0xb0014
; SI-NEXT: s_add_i32 s10, s8, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[8:9], s[0:1], s10
; SI-NEXT: s_andn2_b64 s[8:9], s[16:17], s[8:9]
; SI-NEXT: s_and_b32 s11, s17, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s10, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s11, s9
; SI-NEXT: s_cmp_gt_i32 s10, 51
; SI-NEXT: s_cselect_b32 s29, s17, s9
; SI-NEXT: s_cselect_b32 s28, s16, s8
; SI-NEXT: v_mov_b32_e32 v0, s28
; SI-NEXT: v_mov_b32_e32 v1, s29
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[0:1]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[16:17], 0
; SI-NEXT: v_add_f64 v[0:1], s[6:7], v[16:17]
; SI-NEXT: s_and_b64 s[6:7], s[8:9], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s39, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s23, 0xb0014
; SI-NEXT: s_add_i32 s8, s6, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; SI-NEXT: s_andn2_b64 s[6:7], s[22:23], s[6:7]
; SI-NEXT: s_and_b32 s9, s23, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s9, s7
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: s_cselect_b32 s27, s23, s7
; SI-NEXT: s_cselect_b32 s26, s22, s6
; SI-NEXT: v_mov_b32_e32 v4, s26
; SI-NEXT: v_mov_b32_e32 v5, s27
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[4:5]
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[22:23], 0
; SI-NEXT: v_mov_b32_e32 v17, s3
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s21, 0xb0014
; SI-NEXT: s_add_i32 s8, s6, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; SI-NEXT: s_andn2_b64 s[6:7], s[20:21], s[6:7]
; SI-NEXT: s_and_b32 s9, s21, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s8, 0
; SI-NEXT: s_cselect_b32 s6, 0, s6
; SI-NEXT: s_cselect_b32 s7, s9, s7
; SI-NEXT: s_cmp_gt_i32 s8, 51
; SI-NEXT: s_cselect_b32 s7, s21, s7
; SI-NEXT: s_cselect_b32 s6, s20, s6
; SI-NEXT: v_mov_b32_e32 v4, s6
; SI-NEXT: v_mov_b32_e32 v5, s7
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[4:5]
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x39
; SI-NEXT: v_add_f64 v[6:7], s[24:25], v[16:17]
; SI-NEXT: s_and_b64 s[24:25], s[36:37], vcc
; SI-NEXT: s_and_b64 s[24:25], s[24:25], exec
; SI-NEXT: v_mov_b32_e32 v17, s33
; SI-NEXT: s_cselect_b32 s33, 0x3ff00000, 0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_bfe_u32 s24, s11, 0xb0014
; SI-NEXT: v_add_f64 v[4:5], s[34:35], v[16:17]
; SI-NEXT: s_add_i32 s34, s24, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[24:25], s[0:1], s34
; SI-NEXT: s_andn2_b64 s[24:25], s[10:11], s[24:25]
; SI-NEXT: s_and_b32 s35, s11, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s34, 0
; SI-NEXT: s_cselect_b32 s24, 0, s24
; SI-NEXT: s_cselect_b32 s25, s35, s25
; SI-NEXT: s_cmp_gt_i32 s34, 51
; SI-NEXT: s_cselect_b32 s25, s11, s25
; SI-NEXT: s_cselect_b32 s24, s10, s24
; SI-NEXT: v_mov_b32_e32 v8, s24
; SI-NEXT: v_mov_b32_e32 v9, s25
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[10:11], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 s[10:11], s[10:11], 0
; SI-NEXT: v_mov_b32_e32 v17, s38
; SI-NEXT: s_and_b64 s[10:11], s[10:11], vcc
; SI-NEXT: s_and_b64 s[10:11], s[10:11], exec
; SI-NEXT: v_add_f64 v[10:11], s[30:31], v[16:17]
; SI-NEXT: s_cselect_b32 s30, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
; SI-NEXT: s_add_i32 s31, s10, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[10:11], s[0:1], s31
; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[10:11]
; SI-NEXT: s_and_b32 s34, s9, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s31, 0
; SI-NEXT: s_cselect_b32 s10, 0, s10
; SI-NEXT: s_cselect_b32 s11, s34, s11
; SI-NEXT: s_cmp_gt_i32 s31, 51
; SI-NEXT: s_cselect_b32 s11, s9, s11
; SI-NEXT: s_cselect_b32 s10, s8, s10
; SI-NEXT: v_mov_b32_e32 v8, s10
; SI-NEXT: v_mov_b32_e32 v9, s11
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[8:9], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 s[8:9], s[8:9], 0
; SI-NEXT: v_mov_b32_e32 v17, s39
; SI-NEXT: s_and_b64 s[8:9], s[8:9], vcc
; SI-NEXT: s_and_b64 s[8:9], s[8:9], exec
; SI-NEXT: s_cselect_b32 s31, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s8, s15, 0xb0014
; SI-NEXT: s_add_i32 s34, s8, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[8:9], s[0:1], s34
; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[8:9]
; SI-NEXT: s_and_b32 s35, s15, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s34, 0
; SI-NEXT: s_cselect_b32 s8, 0, s8
; SI-NEXT: s_cselect_b32 s9, s35, s9
; SI-NEXT: s_cmp_gt_i32 s34, 51
; SI-NEXT: s_cselect_b32 s9, s15, s9
; SI-NEXT: s_cselect_b32 s8, s14, s8
; SI-NEXT: v_mov_b32_e32 v8, s8
; SI-NEXT: v_mov_b32_e32 v9, s9
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[14:15], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 s[14:15], s[14:15], 0
; SI-NEXT: v_add_f64 v[8:9], s[28:29], v[16:17]
; SI-NEXT: s_and_b64 s[14:15], s[14:15], vcc
; SI-NEXT: s_and_b64 s[14:15], s[14:15], exec
; SI-NEXT: s_cselect_b32 s28, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s14, s13, 0xb0014
; SI-NEXT: s_add_i32 s29, s14, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[14:15], s[0:1], s29
; SI-NEXT: s_andn2_b64 s[14:15], s[12:13], s[14:15]
; SI-NEXT: s_and_b32 s34, s13, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s29, 0
; SI-NEXT: s_cselect_b32 s14, 0, s14
; SI-NEXT: s_cselect_b32 s15, s34, s15
; SI-NEXT: s_cmp_gt_i32 s29, 51
; SI-NEXT: s_cselect_b32 s15, s13, s15
; SI-NEXT: s_cselect_b32 s14, s12, s14
; SI-NEXT: v_mov_b32_e32 v12, s14
; SI-NEXT: v_mov_b32_e32 v13, s15
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[12:13], v[12:13]
; SI-NEXT: v_cmp_gt_f64_e64 s[12:13], s[12:13], 0
; SI-NEXT: v_mov_b32_e32 v17, s3
; SI-NEXT: s_and_b64 s[12:13], s[12:13], vcc
; SI-NEXT: s_and_b64 s[12:13], s[12:13], exec
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s12, s19, 0xb0014
; SI-NEXT: s_add_i32 s29, s12, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[12:13], s[0:1], s29
; SI-NEXT: s_andn2_b64 s[12:13], s[18:19], s[12:13]
; SI-NEXT: s_and_b32 s34, s19, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s29, 0
; SI-NEXT: s_cselect_b32 s12, 0, s12
; SI-NEXT: s_cselect_b32 s13, s34, s13
; SI-NEXT: s_cmp_gt_i32 s29, 51
; SI-NEXT: s_cselect_b32 s13, s19, s13
; SI-NEXT: s_cselect_b32 s12, s18, s12
; SI-NEXT: v_mov_b32_e32 v12, s12
; SI-NEXT: v_mov_b32_e32 v13, s13
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[18:19], v[12:13]
; SI-NEXT: v_cmp_gt_f64_e64 s[18:19], s[18:19], 0
; SI-NEXT: v_add_f64 v[14:15], s[26:27], v[16:17]
; SI-NEXT: s_and_b64 s[18:19], s[18:19], vcc
; SI-NEXT: s_and_b64 s[18:19], s[18:19], exec
; SI-NEXT: s_cselect_b32 s26, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s18, s17, 0xb0014
; SI-NEXT: s_add_i32 s27, s18, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[18:19], s[0:1], s27
; SI-NEXT: s_andn2_b64 s[18:19], s[16:17], s[18:19]
; SI-NEXT: s_and_b32 s29, s17, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s27, 0
; SI-NEXT: s_cselect_b32 s18, 0, s18
; SI-NEXT: s_cselect_b32 s19, s29, s19
; SI-NEXT: s_cmp_gt_i32 s27, 51
; SI-NEXT: s_cselect_b32 s19, s17, s19
; SI-NEXT: s_cselect_b32 s18, s16, s18
; SI-NEXT: v_mov_b32_e32 v12, s18
; SI-NEXT: v_mov_b32_e32 v13, s19
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[16:17], v[12:13]
; SI-NEXT: v_cmp_gt_f64_e64 s[16:17], s[16:17], 0
; SI-NEXT: v_mov_b32_e32 v17, s33
; SI-NEXT: s_and_b64 s[16:17], s[16:17], vcc
; SI-NEXT: s_and_b64 s[16:17], s[16:17], exec
; SI-NEXT: s_cselect_b32 s27, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s16, s23, 0xb0014
; SI-NEXT: s_add_i32 s29, s16, 0xfffffc01
; SI-NEXT: s_lshr_b64 s[16:17], s[0:1], s29
; SI-NEXT: s_andn2_b64 s[16:17], s[22:23], s[16:17]
; SI-NEXT: s_and_b32 s33, s23, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s29, 0
; SI-NEXT: s_cselect_b32 s17, s33, s17
; SI-NEXT: s_cselect_b32 s16, 0, s16
; SI-NEXT: s_cmp_gt_i32 s29, 51
; SI-NEXT: s_cselect_b32 s17, s23, s17
; SI-NEXT: s_cselect_b32 s16, s22, s16
; SI-NEXT: v_mov_b32_e32 v12, s16
; SI-NEXT: v_mov_b32_e32 v13, s17
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[22:23], v[12:13]
; SI-NEXT: v_cmp_gt_f64_e64 s[22:23], s[22:23], 0
; SI-NEXT: v_add_f64 v[12:13], s[6:7], v[16:17]
; SI-NEXT: s_and_b64 s[6:7], s[22:23], vcc
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: s_cselect_b32 s22, 0x3ff00000, 0
; SI-NEXT: s_bfe_u32 s6, s21, 0xb0014
; SI-NEXT: s_addk_i32 s6, 0xfc01
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s6
; SI-NEXT: s_andn2_b64 s[0:1], s[20:21], s[0:1]
; SI-NEXT: s_and_b32 s7, s21, 0x80000000
; SI-NEXT: s_cmp_lt_i32 s6, 0
; SI-NEXT: s_cselect_b32 s1, s7, s1
; SI-NEXT: s_cselect_b32 s0, 0, s0
; SI-NEXT: s_cmp_gt_i32 s6, 51
; SI-NEXT: v_mov_b32_e32 v17, s30
; SI-NEXT: s_cselect_b32 s1, s21, s1
; SI-NEXT: s_cselect_b32 s0, s20, s0
; SI-NEXT: v_mov_b32_e32 v19, s1
; SI-NEXT: v_mov_b32_e32 v18, s0
; SI-NEXT: v_add_f64 v[20:21], s[24:25], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s31
; SI-NEXT: v_cmp_lg_f64_e32 vcc, s[20:21], v[18:19]
; SI-NEXT: v_add_f64 v[18:19], s[10:11], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s28
; SI-NEXT: v_cmp_gt_f64_e64 s[6:7], s[20:21], 0
; SI-NEXT: v_add_f64 v[24:25], s[8:9], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s3
; SI-NEXT: v_add_f64 v[22:23], s[14:15], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s26
; SI-NEXT: s_and_b64 s[6:7], s[6:7], vcc
; SI-NEXT: v_add_f64 v[28:29], s[12:13], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s27
; SI-NEXT: s_and_b64 s[6:7], s[6:7], exec
; SI-NEXT: v_add_f64 v[26:27], s[18:19], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s22
; SI-NEXT: s_cselect_b32 s3, 0x3ff00000, 0
; SI-NEXT: v_add_f64 v[32:33], s[16:17], v[16:17]
; SI-NEXT: v_mov_b32_e32 v17, s3
; SI-NEXT: v_add_f64 v[30:31], s[0:1], v[16:17]
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dwordx4 v[30:33], off, s[0:3], 0 offset:112
; SI-NEXT: buffer_store_dwordx4 v[26:29], off, s[0:3], 0 offset:96
; SI-NEXT: buffer_store_dwordx4 v[22:25], off, s[0:3], 0 offset:80
; SI-NEXT: buffer_store_dwordx4 v[18:21], off, s[0:3], 0 offset:64
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
store <16 x double> %y, ptr addrspace(1) %out
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CI: {{.*}}
; FUNC: {{.*}}