| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck -check-prefix=SDAG %s |
| ; RUN: llc -global-isel=1 -mtriple=amdgpu7.00-amd-amdhsa -o - %s | FileCheck -check-prefix=GISEL %s |
| |
| define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { |
| ; SDAG-LABEL: v_sdiv_v2i128_vv: |
| ; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v24, 31, v3 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v0, v24 |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v1, v24 |
| ; SDAG-NEXT: v_sub_i32_e32 v16, vcc, v0, v24 |
| ; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v1, v24, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v2, v24 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v25, 31, v11 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v3, v24 |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v1, v24, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v0, v24, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v8, v25 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v9, v25 |
| ; SDAG-NEXT: v_sub_i32_e32 v28, vcc, v1, v25 |
| ; SDAG-NEXT: v_subb_u32_e32 v29, vcc, v0, v25, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v10, v25 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v11, v25 |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v1, v25, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v0, v25, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v1, v29, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v28, v2 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; SDAG-NEXT: v_or_b32_e32 v1, v17, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v16, v18 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v0, v2 |
| ; SDAG-NEXT: v_add_i32_e64 v0, s[6:7], 32, v0 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v3 |
| ; SDAG-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v28 |
| ; SDAG-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v8, v29 |
| ; SDAG-NEXT: v_min_u32_e32 v1, v1, v8 |
| ; SDAG-NEXT: v_add_i32_e64 v1, s[6:7], 64, v1 |
| ; SDAG-NEXT: v_addc_u32_e64 v8, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[2:3] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v10, v17 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[6:7] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v18 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v9, v8, 0, s[6:7] |
| ; SDAG-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v8, v19 |
| ; SDAG-NEXT: v_min_u32_e32 v1, v1, v8 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v8, v16 |
| ; SDAG-NEXT: v_add_i32_e64 v8, s[6:7], 32, v8 |
| ; SDAG-NEXT: v_min_u32_e32 v8, v8, v10 |
| ; SDAG-NEXT: v_add_i32_e64 v8, s[6:7], 64, v8 |
| ; SDAG-NEXT: v_addc_u32_e64 v10, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[18:19] |
| ; SDAG-NEXT: s_mov_b64 s[8:9], 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v1, v8, v1, s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, s[6:7] |
| ; SDAG-NEXT: v_sub_i32_e64 v8, s[6:7], v0, v1 |
| ; SDAG-NEXT: v_subb_u32_e64 v9, s[6:7], v9, v10, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v10, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v11, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_xor_b32_e32 v0, 0x7f, v8 |
| ; SDAG-NEXT: v_cmp_lt_u64_e64 s[8:9], s[8:9], v[8:9] |
| ; SDAG-NEXT: v_or_b32_e32 v0, v0, v10 |
| ; SDAG-NEXT: v_or_b32_e32 v1, v9, v11 |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[0:1] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[10:11] |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[10:11] |
| ; SDAG-NEXT: v_mov_b32_e32 v26, v24 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[8:9] |
| ; SDAG-NEXT: v_and_b32_e32 v0, 1, v0 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[10:11], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v1, v19, 0, s[4:5] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, v18, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[10:11], s[10:11], s[6:7] |
| ; SDAG-NEXT: v_mov_b32_e32 v27, v25 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v17, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v16, 0, s[4:5] |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[10:11] |
| ; SDAG-NEXT: s_cbranch_execz .LBB0_6 |
| ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v9, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v10, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v33, s[4:5], 0, v11, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v11, vcc, s8, v8 |
| ; SDAG-NEXT: v_sub_i32_e32 v9, vcc, 64, v11 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[18:19], v11 |
| ; SDAG-NEXT: v_lshr_b64 v[9:10], v[16:17], v9 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_or_b32_e32 v9, v0, v9 |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, 63, v8 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v1, v10 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[16:17], v0 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[8:9], v[16:17], v11 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v19, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v18, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v10, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v11, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB0_5 |
| ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v30 |
| ; SDAG-NEXT: v_lshr_b64 v[10:11], v[16:17], v30 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[18:19], v20 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v10, v20 |
| ; SDAG-NEXT: v_subrev_i32_e32 v10, vcc, 64, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v21, v11, v21 |
| ; SDAG-NEXT: v_lshr_b64 v[10:11], v[18:19], v10 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v30 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v11, v11, v21, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v11, v17, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, v10, v20, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[10:11], v[18:19], v30 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v20, v16, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v21, 0, v11, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, 0, v10, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v28 |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v29, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v18, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: s_mov_b64 s[4:5], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v11, 0 |
| ; SDAG-NEXT: .LBB0_3: ; %udiv-do-while3 |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[38:39], v[8:9], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v8, v22, v38 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v17 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v22 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v22 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v34, v16 |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v35, v17, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v36, v20, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v37, v21, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v38, 31, v22 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v9, v23, v39 |
| ; SDAG-NEXT: v_and_b32_e32 v23, v38, v28 |
| ; SDAG-NEXT: v_and_b32_e32 v22, v38, v29 |
| ; SDAG-NEXT: v_sub_i32_e32 v16, vcc, v16, v23 |
| ; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v22, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v23, v38, v2 |
| ; SDAG-NEXT: v_and_b32_e32 v22, v38, v3 |
| ; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v20, v23, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v22, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v23, v31, v33 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v30, v32 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23] |
| ; SDAG-NEXT: v_or_b32_e32 v0, v0, v10 |
| ; SDAG-NEXT: v_and_b32_e32 v10, 1, v38 |
| ; SDAG-NEXT: v_or_b32_e32 v1, v19, v1 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v18, v0 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v11 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, v10 |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB0_3 |
| ; SDAG-NEXT: ; %bb.4: ; %Flow13 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: .LBB0_5: ; %Flow14 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[8:9], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v0, v16 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v11, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v21, v10, v2 |
| ; SDAG-NEXT: .LBB0_6: ; %Flow16 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v18, 31, v7 |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v4, v18 |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v5, v18 |
| ; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v3, v18 |
| ; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v2, v18, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v6, v18 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v19, 31, v15 |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v7, v18 |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v3, v18, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v2, v18, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v12, v19 |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v13, v19 |
| ; SDAG-NEXT: v_sub_i32_e32 v28, vcc, v3, v19 |
| ; SDAG-NEXT: v_subb_u32_e32 v29, vcc, v2, v19, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v14, v19 |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v15, v19 |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v19, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v19, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v5, v29, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v4, v28, v2 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] |
| ; SDAG-NEXT: v_or_b32_e32 v5, v9, v7 |
| ; SDAG-NEXT: v_or_b32_e32 v4, v8, v6 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[4:5] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v4, v2 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_add_i32_e32 v4, vcc, 32, v4 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v5, v3 |
| ; SDAG-NEXT: v_min_u32_e32 v4, v4, v5 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v5, v28 |
| ; SDAG-NEXT: v_add_i32_e32 v5, vcc, 32, v5 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v10, v29 |
| ; SDAG-NEXT: v_min_u32_e32 v5, v5, v10 |
| ; SDAG-NEXT: v_add_i32_e32 v5, vcc, 64, v5 |
| ; SDAG-NEXT: v_addc_u32_e64 v10, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v11, v7 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc |
| ; SDAG-NEXT: v_ffbh_u32_e32 v5, v6 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v5, vcc, 32, v5 |
| ; SDAG-NEXT: v_min_u32_e32 v5, v5, v11 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v11, v8 |
| ; SDAG-NEXT: v_add_i32_e32 v11, vcc, 32, v11 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v12, v9 |
| ; SDAG-NEXT: v_min_u32_e32 v11, v11, v12 |
| ; SDAG-NEXT: v_add_i32_e32 v11, vcc, 64, v11 |
| ; SDAG-NEXT: v_addc_u32_e64 v12, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] |
| ; SDAG-NEXT: v_mov_b32_e32 v22, v18 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v5 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v10, v12, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v12, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v13, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f |
| ; SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[4:5] |
| ; SDAG-NEXT: v_or_b32_e32 v15, v5, v13 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[12:13] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v10, 1, v10 |
| ; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10 |
| ; SDAG-NEXT: v_xor_b32_e32 v10, 0x7f, v4 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v10, v12 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] |
| ; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v7, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v6, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v14, v9, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v15, v8, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB0_12 |
| ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v4 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v5, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v12, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v33, s[4:5], 0, v13, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v14, vcc, s8, v4 |
| ; SDAG-NEXT: v_sub_i32_e32 v5, vcc, 64, v14 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[6:7], v14 |
| ; SDAG-NEXT: v_lshr_b64 v[12:13], v[8:9], v5 |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, 63, v4 |
| ; SDAG-NEXT: v_lshl_b64 v[4:5], v[8:9], v4 |
| ; SDAG-NEXT: v_or_b32_e32 v11, v11, v13 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v12 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v5, v7, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v10, v4, v10, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[4:5], v[8:9], v14 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, v6, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v12, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v13, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB0_11 |
| ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader |
| ; SDAG-NEXT: v_sub_i32_e32 v14, vcc, 64, v30 |
| ; SDAG-NEXT: v_lshr_b64 v[12:13], v[8:9], v30 |
| ; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], v14 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v12, v14 |
| ; SDAG-NEXT: v_subrev_i32_e32 v12, vcc, 64, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v15, v13, v15 |
| ; SDAG-NEXT: v_lshr_b64 v[12:13], v[6:7], v12 |
| ; SDAG-NEXT: v_lshr_b64 v[6:7], v[6:7], v30 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v30 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v7, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v6, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v28 |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v29, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v2, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v9, v13, v9, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v8, v12, v8, s[4:5] |
| ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v3, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v6, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v7, 0 |
| ; SDAG-NEXT: s_mov_b64 s[10:11], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v14, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v15, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v13, 0 |
| ; SDAG-NEXT: .LBB0_9: ; %udiv-do-while |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[38:39], v[4:5], 1 |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v4, v14, v38 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v14, 31, v9 |
| ; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v5 |
| ; SDAG-NEXT: v_or_b32_e32 v5, v15, v39 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v15, 31, v11 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v8, v8, v15 |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v12 |
| ; SDAG-NEXT: v_sub_i32_e32 v12, vcc, v34, v8 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v14 |
| ; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v35, v9, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v36, v16, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v14, v30, v32 |
| ; SDAG-NEXT: v_or_b32_e32 v15, v31, v33 |
| ; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v37, v17, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[14:15] |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v14, 31, v12 |
| ; SDAG-NEXT: v_and_b32_e32 v38, v14, v28 |
| ; SDAG-NEXT: v_and_b32_e32 v15, v14, v29 |
| ; SDAG-NEXT: v_sub_i32_e32 v8, vcc, v8, v38 |
| ; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v9, v15, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v39, v14, v2 |
| ; SDAG-NEXT: v_and_b32_e32 v12, 1, v14 |
| ; SDAG-NEXT: v_and_b32_e32 v38, v14, v3 |
| ; SDAG-NEXT: v_subb_u32_e32 v16, vcc, v16, v39, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v11, v7, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v6, v10 |
| ; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11] |
| ; SDAG-NEXT: v_mov_b32_e32 v15, v13 |
| ; SDAG-NEXT: v_mov_b32_e32 v14, v12 |
| ; SDAG-NEXT: v_subb_u32_e32 v17, vcc, v17, v38, vcc |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB0_9 |
| ; SDAG-NEXT: ; %bb.10: ; %Flow |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: .LBB0_11: ; %Flow11 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[4:5], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v6, 31, v5 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v6 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v13, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v15, v12, v2 |
| ; SDAG-NEXT: .LBB0_12: ; %Flow12 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v25, v24 |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v27, v26 |
| ; SDAG-NEXT: v_xor_b32_e32 v5, v0, v2 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v21, v2 |
| ; SDAG-NEXT: v_xor_b32_e32 v4, v1, v3 |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v20, v3 |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v5, v2, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v6, v19, v18 |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v4, v3, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v7, v23, v22 |
| ; SDAG-NEXT: v_xor_b32_e32 v4, v15, v6 |
| ; SDAG-NEXT: v_xor_b32_e32 v5, v14, v7 |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v6 |
| ; SDAG-NEXT: v_xor_b32_e32 v9, v10, v6 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v7, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v8, v11, v7 |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v9, v6, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v8, v7, vcc |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_sdiv_v2i128_vv: |
| ; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v24, 31, v3 |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v24, v0 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v24, v1 |
| ; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v0, v24 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v24, v2 |
| ; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v1, v24, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v25, 31, v11 |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v24, v3 |
| ; GISEL-NEXT: v_subb_u32_e32 v18, vcc, v2, v24, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v19, vcc, v3, v24, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v25, v8 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v25, v9 |
| ; GISEL-NEXT: v_sub_i32_e32 v26, vcc, v0, v25 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v25, v10 |
| ; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v1, v25, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v25, v11 |
| ; GISEL-NEXT: v_subb_u32_e32 v10, vcc, v2, v25, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v3, v25, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v26, v10 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v27, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v17, v19 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v26 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v0, v27 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; GISEL-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v10 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; GISEL-NEXT: v_add_i32_e64 v0, s[6:7], 64, v0 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11] |
| ; GISEL-NEXT: v_min_u32_e32 v1, v2, v1 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[6:7] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v16 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v17 |
| ; GISEL-NEXT: v_min_u32_e32 v1, v2, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v18 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 64, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v19 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[18:19] |
| ; GISEL-NEXT: v_min_u32_e32 v2, v3, v2 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[6:7] |
| ; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v0, v1 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_mov_b32_e32 v8, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v9, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v2, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cmp_gt_u64_e64 s[8:9], v[0:1], v[8:9] |
| ; GISEL-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_lt_u64_e64 s[8:9], 0, v[2:3] |
| ; GISEL-NEXT: v_xor_b32_e32 v20, 0x7f, v0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[2:3] |
| ; GISEL-NEXT: v_or_b32_e32 v20, v20, v2 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[8:9] |
| ; GISEL-NEXT: v_or_b32_e32 v21, v1, v3 |
| ; GISEL-NEXT: v_and_b32_e32 v8, 1, v8 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[20:21] |
| ; GISEL-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v8 |
| ; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; GISEL-NEXT: s_mov_b64 s[10:11], exec |
| ; GISEL-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_mov_b64 s[12:13], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v20, v16, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v8, v18, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v9, v19, 0, s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[8:9], s[6:7], s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v21, v17, 0, s[4:5] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB0_6 |
| ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; GISEL-NEXT: v_add_i32_e32 v28, vcc, 1, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, 0, v1, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v30, vcc, 0, v2, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, 0, v3, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 0x7f, v0 |
| ; GISEL-NEXT: v_not_b32_e32 v0, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v20, vcc, v22, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v22 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[16:17], v0 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[18:19], v22 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[16:17], v22 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[16:17], v20 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v22 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v20, 0, v8, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v21, 0, v9, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v22 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v8, v0, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v9, v1, v19, vcc |
| ; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s12 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s13 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s14 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s15 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB0_5 |
| ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v28 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[16:17], v28 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[18:19], v2 |
| ; GISEL-NEXT: v_add_i32_e32 v32, vcc, 0xffffffc0, v28 |
| ; GISEL-NEXT: v_lshr_b64 v[22:23], v[18:19], v28 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[18:19], v32 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v28 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v32, vcc, -1, v26 |
| ; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v27, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v28 |
| ; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v0, v16, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, v1, v17, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v11, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v17, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v16, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: .LBB0_3: ; %udiv-do-while3 |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v16, 31, v21 |
| ; GISEL-NEXT: v_or_b32_e32 v20, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v21, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[18:19], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v18, 31, v9 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[22:23], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v18 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v22, 31, v19 |
| ; GISEL-NEXT: v_sub_i32_e32 v18, vcc, v32, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v0, v22 |
| ; GISEL-NEXT: v_subb_u32_e32 v18, vcc, v33, v3, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v18, vcc, v34, v0, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v18, vcc, v35, v1, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v36, 31, v18 |
| ; GISEL-NEXT: v_and_b32_e32 v18, v36, v26 |
| ; GISEL-NEXT: v_and_b32_e32 v19, v36, v27 |
| ; GISEL-NEXT: v_sub_i32_e32 v18, vcc, v2, v18 |
| ; GISEL-NEXT: v_subb_u32_e32 v19, vcc, v3, v19, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v2, v36, v10 |
| ; GISEL-NEXT: v_and_b32_e32 v3, v36, v11 |
| ; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v0, v2, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v23, vcc, v1, v3, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v28, vcc, -1, v28 |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v30, vcc, -1, v30, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v28, v30 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v29, v31 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v8, v8, v16 |
| ; GISEL-NEXT: v_and_b32_e32 v16, 1, v36 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, v16 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, v17 |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB0_3 |
| ; GISEL-NEXT: ; %bb.4: ; %Flow13 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB0_5: ; %Flow14 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v10, 31, v21 |
| ; GISEL-NEXT: v_or_b32_e32 v8, v8, v10 |
| ; GISEL-NEXT: v_or_b32_e32 v20, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v21, v1, v3 |
| ; GISEL-NEXT: .LBB0_6: ; %Flow16 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v18, 31, v7 |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v18, v4 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v18, v5 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v18, v6 |
| ; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v0, v18 |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v18, v7 |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v1, v18, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v19, 31, v15 |
| ; GISEL-NEXT: v_subb_u32_e32 v10, vcc, v2, v18, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v3, v18, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v19, v12 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v19, v13 |
| ; GISEL-NEXT: v_sub_i32_e32 v22, vcc, v0, v19 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v19, v14 |
| ; GISEL-NEXT: v_subb_u32_e32 v23, vcc, v1, v19, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v19, v15 |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v2, v19, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v3, v19, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v22, v4 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v23, v5 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v6, v10 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v7, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v22 |
| ; GISEL-NEXT: s_or_b64 s[10:11], vcc, s[4:5] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v0, v23 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 32, v1 |
| ; GISEL-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v4 |
| ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0 |
| ; GISEL-NEXT: v_add_i32_e32 v2, vcc, 32, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v5 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v6 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v7 |
| ; GISEL-NEXT: v_add_i32_e32 v2, vcc, 32, v2 |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v10 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 64, v1 |
| ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 32, v3 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] |
| ; GISEL-NEXT: v_min_u32_e32 v2, v2, v3 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, vcc |
| ; GISEL-NEXT: v_mov_b32_e32 v12, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v13, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v2, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[12:13] |
| ; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[2:3] |
| ; GISEL-NEXT: s_mov_b64 s[6:7], exec |
| ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v12, 1, v12 |
| ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 |
| ; GISEL-NEXT: v_xor_b32_e32 v12, 0x7f, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v12, v12, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v13, v1, v3 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[12:13] |
| ; GISEL-NEXT: s_or_b64 s[10:11], s[10:11], vcc |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v12, v6, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v13, v7, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v14, v10, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v15, v11, 0, s[10:11] |
| ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; GISEL-NEXT: s_cbranch_execz .LBB0_12 |
| ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, 1, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v27, vcc, 0, v1, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v28, vcc, 0, v2, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, 0, v3, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v14, vcc, 0x7f, v0 |
| ; GISEL-NEXT: v_not_b32_e32 v0, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v14, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v14 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v0 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[10:11], v14 |
| ; GISEL-NEXT: v_lshl_b64 v[12:13], v[6:7], v14 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[6:7], v15 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v14, v0, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v15, v1, v11, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB0_11 |
| ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader |
| ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v26 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v26 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[10:11], v2 |
| ; GISEL-NEXT: v_add_i32_e32 v30, vcc, 0xffffffc0, v26 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[10:11], v26 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[10:11], v30 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v30, vcc, -1, v22 |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v23, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v26 |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v4, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v10, v0, v6, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v11, v1, v7, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v5, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v7, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v6, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: .LBB0_9: ; %udiv-do-while |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[10:11], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v6, 31, v11 |
| ; GISEL-NEXT: v_or_b32_e32 v16, v16, v6 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v6, 31, v15 |
| ; GISEL-NEXT: v_lshl_b64 v[10:11], v[12:13], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v6 |
| ; GISEL-NEXT: v_or_b32_e32 v12, v0, v10 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v30, v2 |
| ; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v31, v3, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v32, v16, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v33, v17, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v26 |
| ; GISEL-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 |
| ; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v6, 31, v13 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v34, 31, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v14, v14, v6 |
| ; GISEL-NEXT: v_and_b32_e32 v6, 1, v34 |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v13, v1, v11 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, v6 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, v7 |
| ; GISEL-NEXT: v_and_b32_e32 v6, v34, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v10, v26, v28 |
| ; GISEL-NEXT: v_or_b32_e32 v11, v27, v29 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] |
| ; GISEL-NEXT: v_and_b32_e32 v11, v34, v23 |
| ; GISEL-NEXT: v_sub_i32_e64 v10, s[4:5], v2, v6 |
| ; GISEL-NEXT: v_and_b32_e32 v35, v34, v4 |
| ; GISEL-NEXT: v_subb_u32_e64 v11, s[4:5], v3, v11, s[4:5] |
| ; GISEL-NEXT: v_and_b32_e32 v34, v34, v5 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_subb_u32_e64 v16, vcc, v16, v35, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v17, v34, vcc |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB0_9 |
| ; GISEL-NEXT: ; %bb.10: ; %Flow |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB0_11: ; %Flow11 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[12:13], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v13 |
| ; GISEL-NEXT: v_or_b32_e32 v14, v14, v4 |
| ; GISEL-NEXT: v_or_b32_e32 v12, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v13, v1, v3 |
| ; GISEL-NEXT: .LBB0_12: ; %Flow12 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v25, v24 |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v20, v3 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v21, v3 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v8, v3 |
| ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v4, v9, v3 |
| ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v3, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v7, v19, v18 |
| ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v4, v3, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v4, v12, v7 |
| ; GISEL-NEXT: v_xor_b32_e32 v5, v13, v7 |
| ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v4, v7 |
| ; GISEL-NEXT: v_xor_b32_e32 v6, v14, v7 |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v7, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v8, v15, v7 |
| ; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v7, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v8, v7, vcc |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = sdiv <2 x i128> %lhs, %rhs |
| ret <2 x i128> %shl |
| } |
| |
| define <2 x i128> @v_sdiv_v2i128_v_pow2k(<2 x i128> %lhs) { |
| ; SDAG-LABEL: v_sdiv_v2i128_v_pow2k: |
| ; SDAG: ; %bb.0: |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v8, 31, v3 |
| ; SDAG-NEXT: v_mov_b32_e32 v9, v8 |
| ; SDAG-NEXT: v_lshr_b64 v[8:9], v[8:9], 31 |
| ; SDAG-NEXT: v_add_i32_e32 v0, vcc, v0, v8 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v8, 31, v7 |
| ; SDAG-NEXT: v_addc_u32_e32 v0, vcc, v1, v9, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v9, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[8:9], v[8:9], 31 |
| ; SDAG-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v4, vcc, v4, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v4, vcc, v5, v9, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc |
| ; SDAG-NEXT: v_alignbit_b32 v0, v1, v0, 1 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v2, 1, v10 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v10 |
| ; SDAG-NEXT: v_alignbit_b32 v4, v5, v4, 1 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v6, 1, v8 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v7, 31, v8 |
| ; SDAG-NEXT: v_alignbit_b32 v1, v10, v1, 1 |
| ; SDAG-NEXT: v_alignbit_b32 v5, v8, v5, 1 |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_sdiv_v2i128_v_pow2k: |
| ; GISEL: ; %bb.0: |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v3 |
| ; GISEL-NEXT: v_mov_b32_e32 v9, v8 |
| ; GISEL-NEXT: v_lshr_b64 v[8:9], v[8:9], 31 |
| ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v8 |
| ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v3, 1, v8 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v8, 31, v7 |
| ; GISEL-NEXT: v_mov_b32_e32 v9, v8 |
| ; GISEL-NEXT: v_lshr_b64 v[8:9], v[8:9], 31 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[1:2], 31 |
| ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 |
| ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v5, v9, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc |
| ; GISEL-NEXT: v_lshl_b64 v[4:5], v[5:6], 31 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v7, 1, v8 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v0, v3 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v2, 1, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v4, v4, v7 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v6 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 1, v6 |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = sdiv <2 x i128> %lhs, <i128 8589934592, i128 8589934592> |
| ret <2 x i128> %shl |
| } |
| |
| define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { |
| ; SDAG-LABEL: v_udiv_v2i128_vv: |
| ; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: v_mov_b32_e32 v19, v3 |
| ; SDAG-NEXT: v_mov_b32_e32 v18, v2 |
| ; SDAG-NEXT: v_or_b32_e32 v3, v9, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v2, v8, v10 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] |
| ; SDAG-NEXT: v_or_b32_e32 v3, v1, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v2, v0, v18 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v2, v10 |
| ; SDAG-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v3, v11 |
| ; SDAG-NEXT: v_min_u32_e32 v2, v2, v3 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v3, v8 |
| ; SDAG-NEXT: v_add_i32_e64 v3, s[6:7], 32, v3 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v9 |
| ; SDAG-NEXT: v_min_u32_e32 v3, v3, v16 |
| ; SDAG-NEXT: v_add_i32_e64 v3, s[6:7], 64, v3 |
| ; SDAG-NEXT: v_addc_u32_e64 v16, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[10:11] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[6:7] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v3, v18 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, 0, s[6:7] |
| ; SDAG-NEXT: v_add_i32_e64 v3, s[6:7], 32, v3 |
| ; SDAG-NEXT: v_min_u32_e32 v3, v3, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v0 |
| ; SDAG-NEXT: v_add_i32_e64 v17, s[6:7], 32, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v20, v1 |
| ; SDAG-NEXT: v_min_u32_e32 v17, v17, v20 |
| ; SDAG-NEXT: v_add_i32_e64 v17, s[6:7], 64, v17 |
| ; SDAG-NEXT: v_addc_u32_e64 v20, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[18:19] |
| ; SDAG-NEXT: s_mov_b64 s[8:9], 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v20, 0, s[6:7] |
| ; SDAG-NEXT: v_sub_i32_e64 v20, s[6:7], v2, v3 |
| ; SDAG-NEXT: v_subb_u32_e64 v21, s[6:7], v16, v21, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v22, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v23, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_xor_b32_e32 v2, 0x7f, v20 |
| ; SDAG-NEXT: v_cmp_lt_u64_e64 s[8:9], s[8:9], v[20:21] |
| ; SDAG-NEXT: v_or_b32_e32 v2, v2, v22 |
| ; SDAG-NEXT: v_or_b32_e32 v3, v21, v23 |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[2:3] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[22:23] |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[22:23] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[8:9] |
| ; SDAG-NEXT: v_and_b32_e32 v2, 1, v2 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v2 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[10:11], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v3, v19, 0, s[4:5] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v2, v18, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[10:11], s[10:11], s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v1, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v0, 0, s[4:5] |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[10:11] |
| ; SDAG-NEXT: s_cbranch_execz .LBB2_6 |
| ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; SDAG-NEXT: v_add_i32_e32 v26, vcc, 1, v20 |
| ; SDAG-NEXT: v_addc_u32_e32 v27, vcc, 0, v21, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v28, vcc, 0, v22, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v29, s[4:5], 0, v23, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v21, vcc, s8, v20 |
| ; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 64, v21 |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[18:19], v21 |
| ; SDAG-NEXT: v_lshr_b64 v[16:17], v[0:1], v16 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v2, v16 |
| ; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 63, v20 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v3, v17 |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v21 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[0:1], v21 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v21 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v3, v3, v19, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v2, v2, v18, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v20, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v21, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB2_5 |
| ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 64, v26 |
| ; SDAG-NEXT: v_lshr_b64 v[20:21], v[0:1], v26 |
| ; SDAG-NEXT: v_lshl_b64 v[22:23], v[18:19], v22 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v26 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v20, v22 |
| ; SDAG-NEXT: v_subrev_i32_e32 v20, vcc, 64, v26 |
| ; SDAG-NEXT: v_or_b32_e32 v23, v21, v23 |
| ; SDAG-NEXT: v_lshr_b64 v[20:21], v[18:19], v20 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[18:19], v26 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v21, v21, v23, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v23, v21, v1, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v1, v20, v22, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, 0, v19, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v9, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v10, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v22, v1, v0, s[4:5] |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v11, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v0, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v1, 0 |
| ; SDAG-NEXT: s_mov_b64 s[4:5], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v24, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v25, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v21, 0 |
| ; SDAG-NEXT: .LBB2_3: ; %udiv-do-while3 |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v17 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v24, v16 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v23 |
| ; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v18, v24 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v22, v24 |
| ; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v30, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v31, v23, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v32, v18, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v33, v19, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v34, 31, v24 |
| ; SDAG-NEXT: v_and_b32_e32 v24, v34, v8 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v22, v24 |
| ; SDAG-NEXT: v_and_b32_e32 v24, v34, v9 |
| ; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v24, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v24, v34, v10 |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v18, v24, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v24, v34, v11 |
| ; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v19, v24, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v26, vcc, -1, v26 |
| ; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v17, v25, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v24, v26, v28 |
| ; SDAG-NEXT: v_or_b32_e32 v25, v27, v29 |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[24:25] |
| ; SDAG-NEXT: v_or_b32_e32 v2, v2, v20 |
| ; SDAG-NEXT: v_and_b32_e32 v20, 1, v34 |
| ; SDAG-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_mov_b32_e32 v25, v21 |
| ; SDAG-NEXT: v_mov_b32_e32 v24, v20 |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB2_3 |
| ; SDAG-NEXT: ; %bb.4: ; %Flow13 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: .LBB2_5: ; %Flow14 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[16:17], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v8, 31, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v2, v2, v8 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v21, v1 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v20, v0 |
| ; SDAG-NEXT: .LBB2_6: ; %Flow16 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_or_b32_e32 v1, v13, v15 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v12, v14 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; SDAG-NEXT: v_or_b32_e32 v1, v5, v7 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v4, v6 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v0, v14 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_add_i32_e32 v0, vcc, 32, v0 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v15 |
| ; SDAG-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v12 |
| ; SDAG-NEXT: v_add_i32_e32 v1, vcc, 32, v1 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v8, v13 |
| ; SDAG-NEXT: v_min_u32_e32 v1, v1, v8 |
| ; SDAG-NEXT: v_add_i32_e32 v1, vcc, 64, v1 |
| ; SDAG-NEXT: v_addc_u32_e64 v8, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v9, v7 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc |
| ; SDAG-NEXT: v_ffbh_u32_e32 v1, v6 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v1, vcc, 32, v1 |
| ; SDAG-NEXT: v_min_u32_e32 v1, v1, v9 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v9, v4 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, 32, v9 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v10, v5 |
| ; SDAG-NEXT: v_min_u32_e32 v9, v9, v10 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, 64, v9 |
| ; SDAG-NEXT: v_addc_u32_e64 v10, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v8, v10, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v18, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v19, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f |
| ; SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] |
| ; SDAG-NEXT: v_or_b32_e32 v11, v1, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v8, 1, v8 |
| ; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8 |
| ; SDAG-NEXT: v_xor_b32_e32 v8, 0x7f, v0 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v8, v18 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] |
| ; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v9, v7, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v8, v6, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v5, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v4, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB2_12 |
| ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, 1, v0 |
| ; SDAG-NEXT: v_addc_u32_e32 v24, vcc, 0, v1, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v25, vcc, 0, v18, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v26, s[4:5], 0, v19, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v8, vcc, s8, v0 |
| ; SDAG-NEXT: v_sub_i32_e32 v1, vcc, 64, v8 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[6:7], v8 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[4:5], v1 |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[4:5], v0 |
| ; SDAG-NEXT: v_or_b32_e32 v11, v11, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v18 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[4:5], v8 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v18, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v10, 0, v10, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB2_11 |
| ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader |
| ; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 64, v9 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[4:5], v9 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[6:7], v8 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v18, v20 |
| ; SDAG-NEXT: v_subrev_i32_e32 v18, vcc, 64, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v8, v19, v21 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[6:7], v18 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v9 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v8, v19, v8, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, v5, s[4:5] |
| ; SDAG-NEXT: v_lshr_b64 v[5:6], v[6:7], v9 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v18, v18, v20, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v21, 0, v6, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, 0, v5, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v6, vcc, -1, v12 |
| ; SDAG-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v7, v18, v4, s[4:5] |
| ; SDAG-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v4, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v5, 0 |
| ; SDAG-NEXT: s_mov_b64 s[10:11], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: .LBB2_9: ; %udiv-do-while |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v8 |
| ; SDAG-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v18 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v1 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v7, v7, v18 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v0, v18 |
| ; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v6, v7 |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v27, v8, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v28, v20, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v29, v21, vcc |
| ; SDAG-NEXT: v_add_i32_e64 v9, s[4:5], -1, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v22, v10 |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v22, 31, v18 |
| ; SDAG-NEXT: v_addc_u32_e64 v24, s[4:5], -1, v24, s[4:5] |
| ; SDAG-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; SDAG-NEXT: v_and_b32_e32 v18, 1, v22 |
| ; SDAG-NEXT: v_and_b32_e32 v30, v22, v15 |
| ; SDAG-NEXT: v_and_b32_e32 v31, v22, v14 |
| ; SDAG-NEXT: v_and_b32_e32 v23, v22, v13 |
| ; SDAG-NEXT: v_and_b32_e32 v22, v22, v12 |
| ; SDAG-NEXT: v_addc_u32_e64 v25, s[4:5], -1, v25, s[4:5] |
| ; SDAG-NEXT: v_sub_i32_e32 v7, vcc, v7, v22 |
| ; SDAG-NEXT: v_addc_u32_e64 v26, s[4:5], -1, v26, s[4:5] |
| ; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v8, v23, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v23, v24, v26 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v9, v25 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[22:23] |
| ; SDAG-NEXT: v_subb_u32_e32 v20, vcc, v20, v31, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v1, v5, v1 |
| ; SDAG-NEXT: v_or_b32_e32 v0, v4, v0 |
| ; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v30, vcc |
| ; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11] |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v19 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, v18 |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB2_9 |
| ; SDAG-NEXT: ; %bb.10: ; %Flow |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: .LBB2_11: ; %Flow11 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[0:1], v[10:11], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v8, v8, v4 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v19, v1 |
| ; SDAG-NEXT: v_or_b32_e32 v11, v18, v0 |
| ; SDAG-NEXT: .LBB2_12: ; %Flow12 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_mov_b32_e32 v0, v17 |
| ; SDAG-NEXT: v_mov_b32_e32 v1, v16 |
| ; SDAG-NEXT: v_mov_b32_e32 v4, v11 |
| ; SDAG-NEXT: v_mov_b32_e32 v5, v10 |
| ; SDAG-NEXT: v_mov_b32_e32 v6, v8 |
| ; SDAG-NEXT: v_mov_b32_e32 v7, v9 |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_udiv_v2i128_vv: |
| ; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_mov_b32_e32 v16, v2 |
| ; GISEL-NEXT: v_mov_b32_e32 v17, v3 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v8, v10 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v9, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v8 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v9 |
| ; GISEL-NEXT: v_add_i32_e64 v3, s[6:7], 32, v3 |
| ; GISEL-NEXT: v_min_u32_e32 v2, v2, v3 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v10 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 64, v2 |
| ; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], 32, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11] |
| ; GISEL-NEXT: v_min_u32_e32 v3, v3, v18 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v3, v2, s[6:7] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v0 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v1 |
| ; GISEL-NEXT: v_add_i32_e64 v3, s[6:7], 32, v3 |
| ; GISEL-NEXT: v_min_u32_e32 v2, v2, v3 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v19, v16 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 64, v2 |
| ; GISEL-NEXT: v_add_i32_e64 v19, s[6:7], 32, v19 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[16:17] |
| ; GISEL-NEXT: v_min_u32_e32 v3, v3, v19 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, v3, v2, s[6:7] |
| ; GISEL-NEXT: v_sub_i32_e64 v20, s[6:7], v18, v19 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v3, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v21, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_subb_u32_e64 v22, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cmp_gt_u64_e64 s[8:9], v[20:21], v[2:3] |
| ; GISEL-NEXT: v_subb_u32_e64 v23, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_lt_u64_e64 s[8:9], 0, v[22:23] |
| ; GISEL-NEXT: v_xor_b32_e32 v18, 0x7f, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[22:23] |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v22 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[8:9] |
| ; GISEL-NEXT: v_or_b32_e32 v19, v21, v23 |
| ; GISEL-NEXT: v_and_b32_e32 v2, 1, v2 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[18:19] |
| ; GISEL-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v2 |
| ; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; GISEL-NEXT: s_mov_b64 s[10:11], exec |
| ; GISEL-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_mov_b64 s[12:13], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v2, v16, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v3, v17, 0, s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[8:9], s[6:7], s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, v1, 0, s[4:5] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB2_6 |
| ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, 1, v20 |
| ; GISEL-NEXT: v_addc_u32_e32 v27, vcc, 0, v21, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v28, vcc, 0, v22, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, 0, v23, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 0x7f, v20 |
| ; GISEL-NEXT: v_not_b32_e32 v2, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v22, vcc, v24, v2 |
| ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v24 |
| ; GISEL-NEXT: v_lshr_b64 v[2:3], v[0:1], v2 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[16:17], v24 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[0:1], v24 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v2, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v3, v19 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[0:1], v22 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v20, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v23, 0, v21, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc |
| ; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s13 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s12 |
| ; GISEL-NEXT: v_mov_b32_e32 v21, s15 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, s14 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB2_5 |
| ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 64, v26 |
| ; GISEL-NEXT: v_add_i32_e32 v30, vcc, 0xffffffc0, v26 |
| ; GISEL-NEXT: v_lshr_b64 v[18:19], v[0:1], v26 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[16:17], v20 |
| ; GISEL-NEXT: v_lshr_b64 v[24:25], v[16:17], v26 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[16:17], v30 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v19, v21 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v24, 0, v24, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v25, 0, v25, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v30, vcc, -1, v8 |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v9, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v26 |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v16, v16, v0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v17, v17, v1, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v11, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v1, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v21, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, s10 |
| ; GISEL-NEXT: .LBB2_3: ; %udiv-do-while3 |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[22:23], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v23 |
| ; GISEL-NEXT: v_or_b32_e32 v22, v18, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v23, v19, v21 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[24:25], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v20, 31, v17 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v20 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v20, 31, v3 |
| ; GISEL-NEXT: v_or_b32_e32 v16, v16, v20 |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, v30, v16 |
| ; GISEL-NEXT: v_subb_u32_e32 v20, vcc, v31, v17, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v20, vcc, v32, v18, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v20, vcc, v33, v19, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v20, 31, v20 |
| ; GISEL-NEXT: v_and_b32_e32 v21, v20, v8 |
| ; GISEL-NEXT: v_and_b32_e32 v24, v20, v9 |
| ; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v16, v21 |
| ; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v17, v24, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v21, v20, v10 |
| ; GISEL-NEXT: v_and_b32_e32 v25, v20, v11 |
| ; GISEL-NEXT: v_subb_u32_e32 v24, vcc, v18, v21, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v19, v25, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v26 |
| ; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v27, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v28, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v29, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v18, v26, v28 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v27, v29 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19] |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v0 |
| ; GISEL-NEXT: v_and_b32_e32 v0, 1, v20 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v19, v1 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, v0 |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB2_3 |
| ; GISEL-NEXT: ; %bb.4: ; %Flow13 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB2_5: ; %Flow14 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[22:23], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v8, 31, v23 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v8 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v19, v1 |
| ; GISEL-NEXT: .LBB2_6: ; %Flow16 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v12, v14 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v13, v15 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v4, v6 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v5, v7 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v12 |
| ; GISEL-NEXT: s_or_b64 s[10:11], vcc, s[4:5] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v0, v13 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 32, v1 |
| ; GISEL-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v8, v14 |
| ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0 |
| ; GISEL-NEXT: v_add_i32_e32 v8, vcc, 32, v8 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v15 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v8 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v8, v4 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v5 |
| ; GISEL-NEXT: v_add_i32_e32 v8, vcc, 32, v8 |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v8 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v9, v6 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 64, v1 |
| ; GISEL-NEXT: v_add_i32_e32 v9, vcc, 32, v9 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v8, v7 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] |
| ; GISEL-NEXT: v_min_u32_e32 v8, v8, v9 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, vcc |
| ; GISEL-NEXT: v_mov_b32_e32 v8, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v9, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v16, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[8:9] |
| ; GISEL-NEXT: v_subb_u32_e64 v17, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[16:17] |
| ; GISEL-NEXT: s_mov_b64 s[6:7], exec |
| ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v8, 1, v8 |
| ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 |
| ; GISEL-NEXT: v_xor_b32_e32 v8, 0x7f, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v8, v8, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v9, v1, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[8:9] |
| ; GISEL-NEXT: s_or_b64 s[10:11], s[10:11], vcc |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v10, v4, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v11, v5, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v8, v6, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v9, v7, 0, s[10:11] |
| ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; GISEL-NEXT: s_cbranch_execz .LBB2_12 |
| ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; GISEL-NEXT: v_add_i32_e32 v24, vcc, 1, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v25, vcc, 0, v1, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v16, vcc, 0, v16, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v17, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v0 |
| ; GISEL-NEXT: v_not_b32_e32 v0, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v21, vcc, v20, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v20 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[4:5], v0 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[6:7], v20 |
| ; GISEL-NEXT: v_lshl_b64 v[10:11], v[4:5], v20 |
| ; GISEL-NEXT: v_or_b32_e32 v22, v0, v8 |
| ; GISEL-NEXT: v_or_b32_e32 v23, v1, v9 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[4:5], v21 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v11, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v23, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v6, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v7, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v21, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v23, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v22, s10 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB2_11 |
| ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 64, v24 |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, 0xffffffc0, v24 |
| ; GISEL-NEXT: v_lshr_b64 v[10:11], v[4:5], v24 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[6:7], v20 |
| ; GISEL-NEXT: v_lshr_b64 v[22:23], v[6:7], v24 |
| ; GISEL-NEXT: v_lshr_b64 v[6:7], v[6:7], v26 |
| ; GISEL-NEXT: v_or_b32_e32 v10, v10, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v11, v11, v21 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v11, 0, v23, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v12 |
| ; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v24 |
| ; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v5, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v21, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v4, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v23, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v22, s10 |
| ; GISEL-NEXT: .LBB2_9: ; %udiv-do-while |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[22:23], v[6:7], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v7 |
| ; GISEL-NEXT: v_or_b32_e32 v10, v10, v4 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v9 |
| ; GISEL-NEXT: v_or_b32_e32 v22, v22, v4 |
| ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v26, v22 |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v27, v23, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v28, v10, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v29, v11, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v24, vcc, -1, v24 |
| ; GISEL-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc |
| ; GISEL-NEXT: v_lshl_b64 v[6:7], v[0:1], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v30, 31, v4 |
| ; GISEL-NEXT: v_addc_u32_e32 v16, vcc, -1, v16, vcc |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1 |
| ; GISEL-NEXT: v_and_b32_e32 v4, 1, v30 |
| ; GISEL-NEXT: v_addc_u32_e32 v17, vcc, -1, v17, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v20, v6 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v21, v7 |
| ; GISEL-NEXT: v_mov_b32_e32 v21, v5 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, v4 |
| ; GISEL-NEXT: v_and_b32_e32 v4, v30, v12 |
| ; GISEL-NEXT: v_or_b32_e32 v6, v24, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v7, v25, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] |
| ; GISEL-NEXT: v_and_b32_e32 v7, v30, v13 |
| ; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v22, v4 |
| ; GISEL-NEXT: v_and_b32_e32 v31, v30, v14 |
| ; GISEL-NEXT: v_subb_u32_e64 v7, s[4:5], v23, v7, s[4:5] |
| ; GISEL-NEXT: v_and_b32_e32 v30, v30, v15 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_subb_u32_e64 v10, vcc, v10, v31, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v11, v30, vcc |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB2_9 |
| ; GISEL-NEXT: ; %bb.10: ; %Flow |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB2_11: ; %Flow11 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[4:5], v[0:1], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1 |
| ; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v10, v20, v4 |
| ; GISEL-NEXT: v_or_b32_e32 v11, v21, v5 |
| ; GISEL-NEXT: .LBB2_12: ; %Flow12 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, v18 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, v19 |
| ; GISEL-NEXT: v_mov_b32_e32 v4, v10 |
| ; GISEL-NEXT: v_mov_b32_e32 v5, v11 |
| ; GISEL-NEXT: v_mov_b32_e32 v6, v8 |
| ; GISEL-NEXT: v_mov_b32_e32 v7, v9 |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = udiv <2 x i128> %lhs, %rhs |
| ret <2 x i128> %shl |
| } |
| |
| define <2 x i128> @v_udiv_v2i128_v_pow2k(<2 x i128> %lhs) { |
| ; SDAG-LABEL: v_udiv_v2i128_v_pow2k: |
| ; SDAG: ; %bb.0: |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v8, 1, v3 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v9, 1, v7 |
| ; SDAG-NEXT: v_alignbit_b32 v0, v2, v1, 1 |
| ; SDAG-NEXT: v_alignbit_b32 v4, v6, v5, 1 |
| ; SDAG-NEXT: v_alignbit_b32 v1, v3, v2, 1 |
| ; SDAG-NEXT: v_alignbit_b32 v5, v7, v6, 1 |
| ; SDAG-NEXT: v_mov_b32_e32 v2, v8 |
| ; SDAG-NEXT: v_mov_b32_e32 v3, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v6, v9 |
| ; SDAG-NEXT: v_mov_b32_e32 v7, 0 |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_udiv_v2i128_v_pow2k: |
| ; GISEL: ; %bb.0: |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_mov_b32_e32 v4, v1 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[2:3], 31 |
| ; GISEL-NEXT: v_mov_b32_e32 v8, v5 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v2, 1, v4 |
| ; GISEL-NEXT: v_lshl_b64 v[4:5], v[6:7], 31 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v0, v2 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v2, 1, v3 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v3, 1, v8 |
| ; GISEL-NEXT: v_or_b32_e32 v4, v4, v3 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v6, 1, v7 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v7, 0 |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = udiv <2 x i128> %lhs, <i128 8589934592, i128 8589934592> |
| ret <2 x i128> %shl |
| } |
| |
| define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { |
| ; SDAG-LABEL: v_srem_v2i128_vv: |
| ; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v28, 31, v3 |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v0, v28 |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v1, v28 |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v28 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v28, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v2, v28 |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v3, v28 |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v28, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v16, 31, v11 |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v28, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v8, v8, v16 |
| ; SDAG-NEXT: v_xor_b32_e32 v9, v9, v16 |
| ; SDAG-NEXT: v_sub_i32_e32 v30, vcc, v8, v16 |
| ; SDAG-NEXT: v_subb_u32_e32 v29, vcc, v9, v16, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v8, v10, v16 |
| ; SDAG-NEXT: v_xor_b32_e32 v9, v11, v16 |
| ; SDAG-NEXT: v_subb_u32_e32 v8, vcc, v8, v16, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v9, v16, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v11, v29, v9 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v30, v8 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] |
| ; SDAG-NEXT: v_or_b32_e32 v11, v1, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v0, v2 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v10, v8 |
| ; SDAG-NEXT: v_add_i32_e64 v10, s[6:7], 32, v10 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v11, v9 |
| ; SDAG-NEXT: v_min_u32_e32 v10, v10, v11 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v11, v30 |
| ; SDAG-NEXT: v_add_i32_e64 v11, s[6:7], 32, v11 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v29 |
| ; SDAG-NEXT: v_min_u32_e32 v11, v11, v16 |
| ; SDAG-NEXT: v_add_i32_e64 v11, s[6:7], 64, v11 |
| ; SDAG-NEXT: v_addc_u32_e64 v16, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[8:9] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[6:7] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v11, v2 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v16, 0, s[6:7] |
| ; SDAG-NEXT: v_add_i32_e64 v11, s[6:7], 32, v11 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v3 |
| ; SDAG-NEXT: v_min_u32_e32 v11, v11, v16 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v0 |
| ; SDAG-NEXT: v_add_i32_e64 v16, s[6:7], 32, v16 |
| ; SDAG-NEXT: v_min_u32_e32 v16, v16, v18 |
| ; SDAG-NEXT: v_add_i32_e64 v16, s[6:7], 64, v16 |
| ; SDAG-NEXT: v_addc_u32_e64 v18, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[2:3] |
| ; SDAG-NEXT: s_mov_b64 s[8:9], 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v16, v11, s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v18, v18, 0, s[6:7] |
| ; SDAG-NEXT: v_sub_i32_e64 v16, s[6:7], v10, v11 |
| ; SDAG-NEXT: v_subb_u32_e64 v17, s[6:7], v17, v18, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v18, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v19, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_xor_b32_e32 v10, 0x7f, v16 |
| ; SDAG-NEXT: v_cmp_lt_u64_e64 s[8:9], s[8:9], v[16:17] |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v11, v17, v19 |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[10:11] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[18:19] |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[18:19] |
| ; SDAG-NEXT: v_mov_b32_e32 v31, v28 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[8:9] |
| ; SDAG-NEXT: v_and_b32_e32 v10, 1, v10 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v10 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[10:11], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v3, 0, s[4:5] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v2, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[10:11], s[10:11], s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v35, v1, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v37, v0, 0, s[4:5] |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[10:11] |
| ; SDAG-NEXT: s_cbranch_execz .LBB4_6 |
| ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; SDAG-NEXT: v_add_i32_e32 v32, vcc, 1, v16 |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, 0, v17, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v34, vcc, 0, v18, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v35, s[4:5], 0, v19, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v19, vcc, s8, v16 |
| ; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v19 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[2:3], v19 |
| ; SDAG-NEXT: v_lshr_b64 v[17:18], v[0:1], v17 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v10, v17 |
| ; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 63, v16 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v11, v18 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[0:1], v10 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[0:1], v19 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v11, v11, v3, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, v2, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v18, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB4_5 |
| ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v32 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[0:1], v32 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[2:3], v20 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v32 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v18, v20 |
| ; SDAG-NEXT: v_subrev_i32_e32 v18, vcc, 64, v32 |
| ; SDAG-NEXT: v_or_b32_e32 v21, v19, v21 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[2:3], v18 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v32 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, v19, v21, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v19, v1, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[2:3], v32 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v20, v0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v25, 0, v19, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v24, 0, v18, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v36, vcc, -1, v30 |
| ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v29, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v38, vcc, -1, v8, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v9, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v22, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: s_mov_b64 s[4:5], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v26, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v27, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: .LBB4_3: ; %udiv-do-while3 |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[48:49], v[16:17], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v26, v48 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v26, 31, v21 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v24, v24, v26 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v26, 31, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v26 |
| ; SDAG-NEXT: v_sub_i32_e32 v26, vcc, v36, v20 |
| ; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v37, v21, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v38, v24, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v39, v25, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v48, 31, v26 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v27, v49 |
| ; SDAG-NEXT: v_and_b32_e32 v27, v48, v30 |
| ; SDAG-NEXT: v_and_b32_e32 v26, v48, v29 |
| ; SDAG-NEXT: v_sub_i32_e32 v20, vcc, v20, v27 |
| ; SDAG-NEXT: v_subb_u32_e32 v21, vcc, v21, v26, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v27, v48, v8 |
| ; SDAG-NEXT: v_and_b32_e32 v26, v48, v9 |
| ; SDAG-NEXT: v_subb_u32_e32 v24, vcc, v24, v27, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v26, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v32, vcc, -1, v32 |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v34, vcc, -1, v34, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v27, v33, v35 |
| ; SDAG-NEXT: v_or_b32_e32 v26, v32, v34 |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[26:27] |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v18 |
| ; SDAG-NEXT: v_and_b32_e32 v18, 1, v48 |
| ; SDAG-NEXT: v_or_b32_e32 v11, v23, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v22, v10 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_mov_b32_e32 v27, v19 |
| ; SDAG-NEXT: v_mov_b32_e32 v26, v18 |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB4_3 |
| ; SDAG-NEXT: ; %bb.4: ; %Flow13 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: .LBB4_5: ; %Flow14 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v17 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v10, v10, v20 |
| ; SDAG-NEXT: v_or_b32_e32 v35, v19, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v37, v18, v16 |
| ; SDAG-NEXT: .LBB4_6: ; %Flow16 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v32, 31, v7 |
| ; SDAG-NEXT: v_xor_b32_e32 v4, v4, v32 |
| ; SDAG-NEXT: v_xor_b32_e32 v5, v5, v32 |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v32 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v32, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v6, v6, v32 |
| ; SDAG-NEXT: v_xor_b32_e32 v7, v7, v32 |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v32, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v16, 31, v15 |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v32, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v12, v12, v16 |
| ; SDAG-NEXT: v_xor_b32_e32 v13, v13, v16 |
| ; SDAG-NEXT: v_sub_i32_e32 v36, vcc, v12, v16 |
| ; SDAG-NEXT: v_subb_u32_e32 v33, vcc, v13, v16, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v12, v14, v16 |
| ; SDAG-NEXT: v_xor_b32_e32 v13, v15, v16 |
| ; SDAG-NEXT: v_subb_u32_e32 v12, vcc, v12, v16, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v13, vcc, v13, v16, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v15, v33, v13 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v36, v12 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] |
| ; SDAG-NEXT: v_or_b32_e32 v15, v5, v7 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v4, v6 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[14:15] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v14, v12 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_add_i32_e32 v14, vcc, 32, v14 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v15, v13 |
| ; SDAG-NEXT: v_min_u32_e32 v14, v14, v15 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v15, v36 |
| ; SDAG-NEXT: v_add_i32_e32 v15, vcc, 32, v15 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v33 |
| ; SDAG-NEXT: v_min_u32_e32 v15, v15, v16 |
| ; SDAG-NEXT: v_add_i32_e32 v15, vcc, 64, v15 |
| ; SDAG-NEXT: v_addc_u32_e64 v16, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v7 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc |
| ; SDAG-NEXT: v_ffbh_u32_e32 v15, v6 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, 0, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v15, vcc, 32, v15 |
| ; SDAG-NEXT: v_min_u32_e32 v15, v15, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v4 |
| ; SDAG-NEXT: v_add_i32_e32 v17, vcc, 32, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v5 |
| ; SDAG-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; SDAG-NEXT: v_add_i32_e32 v17, vcc, 64, v17 |
| ; SDAG-NEXT: v_addc_u32_e64 v18, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] |
| ; SDAG-NEXT: v_mov_b32_e32 v34, v32 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v18, v18, 0, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v14, vcc, v14, v15 |
| ; SDAG-NEXT: v_subb_u32_e32 v15, vcc, v16, v18, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v18, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v19, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f |
| ; SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[14:15] |
| ; SDAG-NEXT: v_or_b32_e32 v21, v15, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[18:19] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v16, 1, v16 |
| ; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16 |
| ; SDAG-NEXT: v_xor_b32_e32 v16, 0x7f, v14 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v16, v18 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[20:21] |
| ; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v7, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v6, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v5, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v4, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB4_12 |
| ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; SDAG-NEXT: v_add_i32_e32 v38, vcc, 1, v14 |
| ; SDAG-NEXT: v_addc_u32_e32 v39, vcc, 0, v15, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v48, vcc, 0, v18, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v49, s[4:5], 0, v19, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v19, vcc, s8, v14 |
| ; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v19 |
| ; SDAG-NEXT: v_lshl_b64 v[15:16], v[6:7], v19 |
| ; SDAG-NEXT: v_lshr_b64 v[17:18], v[4:5], v17 |
| ; SDAG-NEXT: v_sub_i32_e32 v14, vcc, 63, v14 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v15, v17 |
| ; SDAG-NEXT: v_lshl_b64 v[14:15], v[4:5], v14 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v15, v15, v16, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v15, v7, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, v14, v18, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[14:15], v[4:5], v19 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, v6, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v18, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB4_11 |
| ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader |
| ; SDAG-NEXT: v_sub_i32_e32 v20, vcc, 64, v38 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[4:5], v38 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[6:7], v20 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v38 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v18, v20 |
| ; SDAG-NEXT: v_subrev_i32_e32 v18, vcc, 64, v38 |
| ; SDAG-NEXT: v_or_b32_e32 v21, v19, v21 |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[6:7], v18 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v38 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, v19, v21, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v25, v19, v5, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, v18, v20, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[18:19], v[6:7], v38 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v24, v20, v4, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v27, 0, v19, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v26, 0, v18, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v50, vcc, -1, v36 |
| ; SDAG-NEXT: v_addc_u32_e32 v51, vcc, -1, v33, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v52, vcc, -1, v12, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v53, vcc, -1, v13, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v20, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v21, 0 |
| ; SDAG-NEXT: s_mov_b64 s[10:11], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v19, 0 |
| ; SDAG-NEXT: .LBB4_9: ; %udiv-do-while |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v25 |
| ; SDAG-NEXT: v_lshl_b64 v[24:25], v[24:25], 1 |
| ; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v38 |
| ; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v54, 31, v17 |
| ; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v39, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v24, v24, v54 |
| ; SDAG-NEXT: v_addc_u32_e32 v48, vcc, -1, v48, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v26, v26, v18 |
| ; SDAG-NEXT: v_sub_i32_e64 v18, s[4:5], v50, v24 |
| ; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v49, vcc |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v55, 31, v15 |
| ; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 |
| ; SDAG-NEXT: v_subb_u32_e64 v18, vcc, v51, v25, s[4:5] |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v52, v26, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v15, v23, v15 |
| ; SDAG-NEXT: v_or_b32_e32 v14, v22, v14 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v38, v48 |
| ; SDAG-NEXT: v_or_b32_e32 v23, v39, v49 |
| ; SDAG-NEXT: v_subb_u32_e32 v18, vcc, v53, v27, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[22:23] |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v22, 31, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v55 |
| ; SDAG-NEXT: v_and_b32_e32 v18, 1, v22 |
| ; SDAG-NEXT: v_and_b32_e32 v54, v22, v13 |
| ; SDAG-NEXT: v_and_b32_e32 v55, v22, v12 |
| ; SDAG-NEXT: v_and_b32_e32 v40, v22, v33 |
| ; SDAG-NEXT: v_and_b32_e32 v22, v22, v36 |
| ; SDAG-NEXT: v_sub_i32_e32 v24, vcc, v24, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v25, vcc, v25, v40, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v55, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v17, v21, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v20, v16 |
| ; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11] |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v19 |
| ; SDAG-NEXT: v_mov_b32_e32 v22, v18 |
| ; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v54, vcc |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB4_9 |
| ; SDAG-NEXT: ; %bb.10: ; %Flow |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: .LBB4_11: ; %Flow11 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v15 |
| ; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v20 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v19, v15 |
| ; SDAG-NEXT: v_or_b32_e32 v21, v18, v14 |
| ; SDAG-NEXT: .LBB4_12: ; %Flow12 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload |
| ; SDAG-NEXT: v_mul_lo_u32 v9, v37, v9 |
| ; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v37, v8, 0 |
| ; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v30, v37, 0 |
| ; SDAG-NEXT: v_mul_lo_u32 v18, v35, v8 |
| ; SDAG-NEXT: v_mov_b32_e32 v24, 0 |
| ; SDAG-NEXT: v_add_i32_e32 v15, vcc, v15, v9 |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v29, v37, v[23:24] |
| ; SDAG-NEXT: v_add_i32_e32 v15, vcc, v15, v18 |
| ; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v10, v30, v[14:15] |
| ; SDAG-NEXT: v_mul_lo_u32 v11, v11, v30 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v8 |
| ; SDAG-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v30, v35, v[23:24] |
| ; SDAG-NEXT: v_mul_lo_u32 v10, v10, v29 |
| ; SDAG-NEXT: v_add_i32_e32 v11, vcc, v11, v15 |
| ; SDAG-NEXT: v_add_i32_e32 v8, vcc, v9, v19 |
| ; SDAG-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, vcc |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v29, v35, v[8:9] |
| ; SDAG-NEXT: v_add_i32_e32 v10, vcc, v10, v11 |
| ; SDAG-NEXT: v_mul_lo_u32 v15, v16, v33 |
| ; SDAG-NEXT: v_add_i32_e32 v8, vcc, v8, v14 |
| ; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v18, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v8, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v0, v0, v28 |
| ; SDAG-NEXT: v_mul_lo_u32 v10, v21, v13 |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v21, v12, 0 |
| ; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v36, v21, 0 |
| ; SDAG-NEXT: v_xor_b32_e32 v1, v1, v31 |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v28 |
| ; SDAG-NEXT: v_xor_b32_e32 v2, v2, v28 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v31, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v3, v3, v31 |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v28, vcc |
| ; SDAG-NEXT: v_mul_lo_u32 v12, v20, v12 |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v31, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v9, v10 |
| ; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v33, v21, v[23:24] |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v9, v12 |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v16, v36, v[8:9] |
| ; SDAG-NEXT: v_mul_lo_u32 v14, v17, v36 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, v10 |
| ; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v36, v20, v[23:24] |
| ; SDAG-NEXT: v_add_i32_e32 v14, vcc, v14, v9 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v11, v13 |
| ; SDAG-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, vcc |
| ; SDAG-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v33, v20, v[9:10] |
| ; SDAG-NEXT: v_add_i32_e32 v11, vcc, v15, v14 |
| ; SDAG-NEXT: v_add_i32_e32 v8, vcc, v9, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v10, v11, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v12, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v8, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v4, v4, v32 |
| ; SDAG-NEXT: v_xor_b32_e32 v5, v5, v34 |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v32 |
| ; SDAG-NEXT: v_xor_b32_e32 v6, v6, v32 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v34, vcc |
| ; SDAG-NEXT: v_xor_b32_e32 v7, v7, v34 |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v32, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v34, vcc |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_srem_v2i128_vv: |
| ; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v29, 31, v3 |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v17, 31, v11 |
| ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v29 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v29 |
| ; GISEL-NEXT: v_xor_b32_e32 v19, v10, v17 |
| ; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v29 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v2, v29 |
| ; GISEL-NEXT: v_xor_b32_e32 v20, v11, v17 |
| ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v1, v29, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v29 |
| ; GISEL-NEXT: v_xor_b32_e32 v16, v8, v17 |
| ; GISEL-NEXT: v_subb_u32_e32 v8, vcc, v2, v29, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v18, v9, v17 |
| ; GISEL-NEXT: v_subb_u32_e32 v9, vcc, v3, v29, vcc |
| ; GISEL-NEXT: v_sub_i32_e32 v31, vcc, v16, v17 |
| ; GISEL-NEXT: v_subb_u32_e32 v30, vcc, v18, v17, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v16, vcc, v19, v17, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v20, v17, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v31, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v30, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v10, v8 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v11, v9 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v31 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v0, v30 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v1 |
| ; GISEL-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v16 |
| ; GISEL-NEXT: v_add_i32_e64 v0, s[6:7], 64, v0 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v17 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[16:17] |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v10 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[6:7] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v11 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v8 |
| ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 |
| ; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 64, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v9 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[8:9] |
| ; GISEL-NEXT: v_min_u32_e32 v2, v3, v2 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[6:7] |
| ; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], v0, v1 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_mov_b32_e32 v18, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v19, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v2, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cmp_gt_u64_e64 s[8:9], v[0:1], v[18:19] |
| ; GISEL-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_lt_u64_e64 s[8:9], 0, v[2:3] |
| ; GISEL-NEXT: v_xor_b32_e32 v20, 0x7f, v0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[2:3] |
| ; GISEL-NEXT: v_or_b32_e32 v20, v20, v2 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v19, v18, s[8:9] |
| ; GISEL-NEXT: v_or_b32_e32 v21, v1, v3 |
| ; GISEL-NEXT: v_and_b32_e32 v18, 1, v18 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[20:21] |
| ; GISEL-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v18 |
| ; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; GISEL-NEXT: s_mov_b64 s[10:11], exec |
| ; GISEL-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_mov_b64 s[12:13], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v28, v10, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v8, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, v9, 0, s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[8:9], s[6:7], s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v33, v11, 0, s[4:5] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB4_6 |
| ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, 0, v1, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v33, vcc, 0, v2, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v34, vcc, 0, v3, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v21, vcc, 0x7f, v0 |
| ; GISEL-NEXT: v_not_b32_e32 v0, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v22, vcc, v21, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v21 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[10:11], v0 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[8:9], v21 |
| ; GISEL-NEXT: v_lshl_b64 v[19:20], v[10:11], v21 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[10:11], v22 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v21 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v19, 0, v19, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v20, 0, v20, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v21 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v21, v0, v8, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v22, v1, v9, vcc |
| ; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s12 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s13 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s14 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s15 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB4_5 |
| ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v18 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[10:11], v18 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[8:9], v2 |
| ; GISEL-NEXT: v_add_i32_e32 v25, vcc, 0xffffffc0, v18 |
| ; GISEL-NEXT: v_lshr_b64 v[23:24], v[8:9], v18 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[8:9], v25 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v23, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v28, 0, v24, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v35, vcc, -1, v31 |
| ; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v30, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 |
| ; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v16, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v25, v0, v10, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v26, v1, v11, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v38, vcc, -1, v17, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v24, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v23, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: .LBB4_3: ; %udiv-do-while3 |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[19:20], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v23, 31, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v20, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[25:26], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v25, 31, v22 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[27:28], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v25 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v27, 31, v26 |
| ; GISEL-NEXT: v_sub_i32_e32 v25, vcc, v35, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v0, v27 |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v36, v3, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v37, v0, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v38, v1, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v39, 31, v25 |
| ; GISEL-NEXT: v_and_b32_e32 v25, v39, v31 |
| ; GISEL-NEXT: v_and_b32_e32 v26, v39, v30 |
| ; GISEL-NEXT: v_sub_i32_e32 v25, vcc, v2, v25 |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v3, v26, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v2, v39, v16 |
| ; GISEL-NEXT: v_and_b32_e32 v3, v39, v17 |
| ; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v0, v2, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v28, vcc, v1, v3, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v18, vcc, -1, v18 |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v34, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v18, v33 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v32, v34 |
| ; GISEL-NEXT: v_lshl_b64 v[21:22], v[21:22], 1 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v21, v21, v23 |
| ; GISEL-NEXT: v_and_b32_e32 v23, 1, v39 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, v23 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, v24 |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB4_3 |
| ; GISEL-NEXT: ; %bb.4: ; %Flow13 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB4_5: ; %Flow14 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[19:20], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[21:22], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v20, 31, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v20 |
| ; GISEL-NEXT: v_or_b32_e32 v28, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v33, v1, v3 |
| ; GISEL-NEXT: .LBB4_6: ; %Flow16 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v32, 31, v7 |
| ; GISEL-NEXT: v_xor_b32_e32 v1, v4, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, v5, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v3, v6, v32 |
| ; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v1, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v5, v7, v32 |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v2, v32, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v15 |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v3, v32, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v12, v12, v0 |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v32, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v13, v13, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v35, vcc, v12, v0 |
| ; GISEL-NEXT: v_xor_b32_e32 v14, v14, v0 |
| ; GISEL-NEXT: v_subb_u32_e32 v34, vcc, v13, v0, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v15, v15, v0 |
| ; GISEL-NEXT: v_subb_u32_e32 v12, vcc, v14, v0, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v13, vcc, v15, v0, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v0, v35, v12 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v34, v13 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] |
| ; GISEL-NEXT: v_or_b32_e32 v0, v6, v4 |
| ; GISEL-NEXT: v_or_b32_e32 v1, v7, v5 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v35 |
| ; GISEL-NEXT: s_or_b64 s[10:11], vcc, s[4:5] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v0, v34 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 32, v1 |
| ; GISEL-NEXT: v_min_u32_e32 v0, v0, v1 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v12 |
| ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0 |
| ; GISEL-NEXT: v_add_i32_e32 v2, vcc, 32, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v13 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[12:13] |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v6 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc |
| ; GISEL-NEXT: v_ffbh_u32_e32 v1, v7 |
| ; GISEL-NEXT: v_add_i32_e32 v2, vcc, 32, v2 |
| ; GISEL-NEXT: v_min_u32_e32 v1, v1, v2 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v3, v4 |
| ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 64, v1 |
| ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 32, v3 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v2, v5 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] |
| ; GISEL-NEXT: v_min_u32_e32 v2, v2, v3 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, vcc |
| ; GISEL-NEXT: v_mov_b32_e32 v2, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v3, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v14, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[0:1], v[2:3] |
| ; GISEL-NEXT: v_subb_u32_e64 v15, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[14:15] |
| ; GISEL-NEXT: s_mov_b64 s[6:7], exec |
| ; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v2, 1, v2 |
| ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; GISEL-NEXT: v_xor_b32_e32 v2, 0x7f, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v14 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v15 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3] |
| ; GISEL-NEXT: s_or_b64 s[10:11], s[10:11], vcc |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v20, v6, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v21, v7, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, 0, s[10:11] |
| ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; GISEL-NEXT: s_cbranch_execz .LBB4_12 |
| ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; GISEL-NEXT: v_add_i32_e32 v36, vcc, 1, v0 |
| ; GISEL-NEXT: v_addc_u32_e32 v37, vcc, 0, v1, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v38, vcc, 0, v14, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v39, vcc, 0, v15, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v0 |
| ; GISEL-NEXT: v_not_b32_e32 v0, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v21, vcc, v20, v0 |
| ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 64, v20 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v0 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[4:5], v20 |
| ; GISEL-NEXT: v_lshl_b64 v[14:15], v[6:7], v20 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[6:7], v21 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v14, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v20, v0, v4, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v21, v1, v5, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB4_11 |
| ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader |
| ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, 64, v36 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[6:7], v36 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[4:5], v2 |
| ; GISEL-NEXT: v_add_i32_e32 v24, vcc, 0xffffffc0, v36 |
| ; GISEL-NEXT: v_lshr_b64 v[22:23], v[4:5], v36 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v3, v1, v3 |
| ; GISEL-NEXT: v_lshr_b64 v[0:1], v[4:5], v24 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v36 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v26, 0, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v23, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v48, vcc, -1, v35 |
| ; GISEL-NEXT: v_addc_u32_e32 v49, vcc, -1, v34, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v36 |
| ; GISEL-NEXT: v_addc_u32_e32 v50, vcc, -1, v12, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v24, v0, v6, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v25, v1, v7, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v51, vcc, -1, v13, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v23, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v0, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v22, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v2, s10 |
| ; GISEL-NEXT: v_mov_b32_e32 v3, s11 |
| ; GISEL-NEXT: .LBB4_9: ; %udiv-do-while |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[14:15], 1 |
| ; GISEL-NEXT: v_add_i32_e32 v36, vcc, -1, v36 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v22, 31, v15 |
| ; GISEL-NEXT: v_or_b32_e32 v14, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v15, v1, v3 |
| ; GISEL-NEXT: v_lshl_b64 v[0:1], v[24:25], 1 |
| ; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v24, 31, v25 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v25, 31, v21 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; GISEL-NEXT: v_addc_u32_e32 v38, vcc, -1, v38, vcc |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[26:27], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v0, v0, v25 |
| ; GISEL-NEXT: v_addc_u32_e32 v39, vcc, -1, v39, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v20, v20, v22 |
| ; GISEL-NEXT: v_sub_i32_e32 v22, vcc, v48, v0 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v24 |
| ; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v49, v1, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v50, v2, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v24, v36, v38 |
| ; GISEL-NEXT: v_or_b32_e32 v25, v37, v39 |
| ; GISEL-NEXT: v_subb_u32_e32 v22, vcc, v51, v3, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[24:25] |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v24, 31, v22 |
| ; GISEL-NEXT: v_and_b32_e32 v25, v24, v35 |
| ; GISEL-NEXT: v_and_b32_e32 v22, 1, v24 |
| ; GISEL-NEXT: v_and_b32_e32 v26, v24, v34 |
| ; GISEL-NEXT: v_and_b32_e32 v27, v24, v12 |
| ; GISEL-NEXT: v_and_b32_e32 v52, v24, v13 |
| ; GISEL-NEXT: v_sub_i32_e32 v24, vcc, v0, v25 |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v1, v26, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v2, v27, vcc |
| ; GISEL-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v0, v22 |
| ; GISEL-NEXT: v_mov_b32_e32 v1, v23 |
| ; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v3, v52, vcc |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB4_9 |
| ; GISEL-NEXT: ; %bb.10: ; %Flow |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB4_11: ; %Flow11 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[22:23], v[14:15], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v14, 31, v15 |
| ; GISEL-NEXT: v_or_b32_e32 v2, v2, v14 |
| ; GISEL-NEXT: v_or_b32_e32 v20, v0, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v21, v1, v23 |
| ; GISEL-NEXT: .LBB4_12: ; %Flow12 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v31, v18, 0 |
| ; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v31, v28, 0 |
| ; GISEL-NEXT: v_mul_lo_u32 v36, v30, v18 |
| ; GISEL-NEXT: v_mul_lo_u32 v3, v35, v3 |
| ; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v33, v[0:1] |
| ; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v35, v2, 0 |
| ; GISEL-NEXT: v_mul_lo_u32 v2, v34, v2 |
| ; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v28, v[14:15] |
| ; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v35, v20, 0 |
| ; GISEL-NEXT: v_mad_u64_u32 v[26:27], vcc, v31, v33, v[23:24] |
| ; GISEL-NEXT: v_mul_lo_u32 v23, v31, v19 |
| ; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v34, v21, v[0:1] |
| ; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v28, v[26:27] |
| ; GISEL-NEXT: v_addc_u32_e64 v23, s[4:5], v25, v23, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v23, vcc, v23, v36, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[24:25], s[4:5], v16, v33, v[23:24] |
| ; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v10, v22 |
| ; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v11, v0, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v22, v10, v29 |
| ; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v17, v28, v[24:25] |
| ; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v12, v20, v[18:19] |
| ; GISEL-NEXT: v_xor_b32_e32 v23, v0, v29 |
| ; GISEL-NEXT: v_subb_u32_e32 v0, vcc, v8, v1, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v9, v10, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[8:9], vcc, v35, v21, v[15:16] |
| ; GISEL-NEXT: v_xor_b32_e32 v18, v0, v29 |
| ; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v22, v29 |
| ; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v34, v20, v[8:9] |
| ; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], v17, v3, s[6:7] |
| ; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v2, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[6:7], v12, v21, v[2:3] |
| ; GISEL-NEXT: v_xor_b32_e32 v19, v1, v29 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v23, v29, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v18, v29, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v19, v29, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[15:16], s[4:5], v13, v20, v[8:9] |
| ; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v6, v14 |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v10, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v4, v11, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v15, vcc |
| ; GISEL-NEXT: v_xor_b32_e32 v6, v6, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v7, v7, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v8, v4, v32 |
| ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v6, v32 |
| ; GISEL-NEXT: v_xor_b32_e32 v9, v5, v32 |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v7, v32, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v8, v32, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v9, v32, vcc |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = srem <2 x i128> %lhs, %rhs |
| ret <2 x i128> %shl |
| } |
| |
| define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { |
| ; SDAG-LABEL: v_urem_v2i128_vv: |
| ; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; SDAG-NEXT: v_or_b32_e32 v17, v9, v11 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v8, v10 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] |
| ; SDAG-NEXT: v_or_b32_e32 v17, v1, v3 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v0, v2 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[16:17] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v16, v10 |
| ; SDAG-NEXT: v_add_i32_e64 v16, s[6:7], 32, v16 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v11 |
| ; SDAG-NEXT: v_min_u32_e32 v16, v16, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v8 |
| ; SDAG-NEXT: v_add_i32_e64 v17, s[6:7], 32, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v9 |
| ; SDAG-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; SDAG-NEXT: v_add_i32_e64 v17, s[6:7], 64, v17 |
| ; SDAG-NEXT: v_addc_u32_e64 v18, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[10:11] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v20, v1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v17, v16, s[6:7] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v17, v2 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v19, v18, 0, s[6:7] |
| ; SDAG-NEXT: v_add_i32_e64 v17, s[6:7], 32, v17 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v3 |
| ; SDAG-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v0 |
| ; SDAG-NEXT: v_add_i32_e64 v18, s[6:7], 32, v18 |
| ; SDAG-NEXT: v_min_u32_e32 v18, v18, v20 |
| ; SDAG-NEXT: v_add_i32_e64 v18, s[6:7], 64, v18 |
| ; SDAG-NEXT: v_addc_u32_e64 v20, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[2:3] |
| ; SDAG-NEXT: s_mov_b64 s[8:9], 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v18, v17, s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v20, 0, s[6:7] |
| ; SDAG-NEXT: v_sub_i32_e64 v18, s[6:7], v16, v17 |
| ; SDAG-NEXT: v_subb_u32_e64 v19, s[6:7], v19, v20, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v20, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_subb_u32_e64 v21, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: v_xor_b32_e32 v16, 0x7f, v18 |
| ; SDAG-NEXT: v_cmp_lt_u64_e64 s[8:9], s[8:9], v[18:19] |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v20 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v19, v21 |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[6:7], 0, v[16:17] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_ne_u64_e64 s[8:9], 0, v[20:21] |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[20:21] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v17, v16, s[8:9] |
| ; SDAG-NEXT: v_and_b32_e32 v16, 1, v16 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v16 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[10:11], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v3, 0, s[4:5] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v2, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[10:11], s[10:11], s[6:7] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v32, v1, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v33, v0, 0, s[4:5] |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[10:11] |
| ; SDAG-NEXT: s_cbranch_execz .LBB5_6 |
| ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v18 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, 0, v19, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, 0, v20, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v33, s[4:5], 0, v21, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v21, vcc, s8, v18 |
| ; SDAG-NEXT: v_sub_i32_e32 v19, vcc, 64, v21 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[2:3], v21 |
| ; SDAG-NEXT: v_lshr_b64 v[19:20], v[0:1], v19 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_or_b32_e32 v19, v16, v19 |
| ; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 63, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v17, v20 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[0:1], v16 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v21 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[0:1], v21 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v21 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v17, v17, v3, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v16, v16, v2, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, 0, v19, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v20, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v21, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB5_5 |
| ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 64, v30 |
| ; SDAG-NEXT: v_lshr_b64 v[20:21], v[0:1], v30 |
| ; SDAG-NEXT: v_lshl_b64 v[22:23], v[2:3], v22 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v20, v22 |
| ; SDAG-NEXT: v_subrev_i32_e32 v20, vcc, 64, v30 |
| ; SDAG-NEXT: v_or_b32_e32 v23, v21, v23 |
| ; SDAG-NEXT: v_lshr_b64 v[20:21], v[2:3], v20 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v30 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v21, v21, v23, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v23, v21, v1, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v22, v20, v22, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[20:21], v[2:3], v30 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v22, v22, v0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v27, 0, v21, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v26, 0, v20, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v9, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v10, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v11, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v24, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v25, 0 |
| ; SDAG-NEXT: s_mov_b64 s[4:5], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v28, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v29, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v21, 0 |
| ; SDAG-NEXT: .LBB5_3: ; %udiv-do-while3 |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[38:39], v[18:19], 1 |
| ; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v28, v38 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v28, 31, v23 |
| ; SDAG-NEXT: v_lshl_b64 v[22:23], v[22:23], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v26, v26, v28 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v28, 31, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v22, v28 |
| ; SDAG-NEXT: v_sub_i32_e32 v28, vcc, v34, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v28, vcc, v35, v23, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v28, vcc, v36, v26, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v28, vcc, v37, v27, vcc |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v38, 31, v28 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v19, v29, v39 |
| ; SDAG-NEXT: v_and_b32_e32 v29, v38, v8 |
| ; SDAG-NEXT: v_and_b32_e32 v28, v38, v9 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v22, v29 |
| ; SDAG-NEXT: v_subb_u32_e32 v23, vcc, v23, v28, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v29, v38, v10 |
| ; SDAG-NEXT: v_and_b32_e32 v28, v38, v11 |
| ; SDAG-NEXT: v_subb_u32_e32 v26, vcc, v26, v29, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v28, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v30, vcc, -1, v30 |
| ; SDAG-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v33, vcc, -1, v33, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v29, v31, v33 |
| ; SDAG-NEXT: v_or_b32_e32 v28, v30, v32 |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[28:29] |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v20 |
| ; SDAG-NEXT: v_and_b32_e32 v20, 1, v38 |
| ; SDAG-NEXT: v_or_b32_e32 v17, v25, v17 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v24, v16 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_mov_b32_e32 v29, v21 |
| ; SDAG-NEXT: v_mov_b32_e32 v28, v20 |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB5_3 |
| ; SDAG-NEXT: ; %bb.4: ; %Flow13 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] |
| ; SDAG-NEXT: .LBB5_5: ; %Flow14 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v19 |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v16, v16, v22 |
| ; SDAG-NEXT: v_or_b32_e32 v32, v21, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v33, v20, v18 |
| ; SDAG-NEXT: .LBB5_6: ; %Flow16 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_or_b32_e32 v19, v13, v15 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v12, v14 |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[18:19] |
| ; SDAG-NEXT: v_or_b32_e32 v19, v5, v7 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v4, v6 |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[18:19] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v18, v14 |
| ; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; SDAG-NEXT: v_add_i32_e32 v18, vcc, 32, v18 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v19, v15 |
| ; SDAG-NEXT: v_min_u32_e32 v18, v18, v19 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v19, v12 |
| ; SDAG-NEXT: v_add_i32_e32 v19, vcc, 32, v19 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v20, v13 |
| ; SDAG-NEXT: v_min_u32_e32 v19, v19, v20 |
| ; SDAG-NEXT: v_add_i32_e32 v19, vcc, 64, v19 |
| ; SDAG-NEXT: v_addc_u32_e64 v20, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] |
| ; SDAG-NEXT: v_ffbh_u32_e32 v21, v7 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc |
| ; SDAG-NEXT: v_ffbh_u32_e32 v19, v6 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v20, 0, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v19, vcc, 32, v19 |
| ; SDAG-NEXT: v_min_u32_e32 v19, v19, v21 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v21, v4 |
| ; SDAG-NEXT: v_add_i32_e32 v21, vcc, 32, v21 |
| ; SDAG-NEXT: v_ffbh_u32_e32 v22, v5 |
| ; SDAG-NEXT: v_min_u32_e32 v21, v21, v22 |
| ; SDAG-NEXT: v_add_i32_e32 v21, vcc, 64, v21 |
| ; SDAG-NEXT: v_addc_u32_e64 v22, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] |
| ; SDAG-NEXT: s_movk_i32 s8, 0x7f |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v22, v22, 0, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v18, vcc, v18, v19 |
| ; SDAG-NEXT: v_subb_u32_e32 v19, vcc, v20, v22, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v22, s[6:7], 0, 0, vcc |
| ; SDAG-NEXT: v_subb_u32_e64 v23, s[6:7], 0, 0, s[6:7] |
| ; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f |
| ; SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[18:19] |
| ; SDAG-NEXT: v_or_b32_e32 v25, v19, v23 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[22:23] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v20, 1, v20 |
| ; SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 1, v20 |
| ; SDAG-NEXT: v_xor_b32_e32 v20, 0x7f, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v24, v20, v22 |
| ; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc |
| ; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[24:25] |
| ; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v7, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v6, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v24, v5, 0, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e64 v25, v4, 0, s[4:5] |
| ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB5_12 |
| ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; SDAG-NEXT: v_add_i32_e32 v34, vcc, 1, v18 |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, 0, v19, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, 0, v22, vcc |
| ; SDAG-NEXT: v_addc_u32_e64 v37, s[4:5], 0, v23, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v23, vcc, s8, v18 |
| ; SDAG-NEXT: v_sub_i32_e32 v21, vcc, 64, v23 |
| ; SDAG-NEXT: v_lshl_b64 v[19:20], v[6:7], v23 |
| ; SDAG-NEXT: v_lshr_b64 v[21:22], v[4:5], v21 |
| ; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 63, v18 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v22 |
| ; SDAG-NEXT: v_or_b32_e32 v22, v19, v21 |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[4:5], v18 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 |
| ; SDAG-NEXT: s_xor_b64 s[8:9], s[4:5], -1 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v23 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v21, v19, v7, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v20, v18, v22, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[4:5], v23 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v20, v20, v6, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v19, 0, v19, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v22, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v18, 0, v18, vcc |
| ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], s[8:9] |
| ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] |
| ; SDAG-NEXT: s_cbranch_execz .LBB5_11 |
| ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader |
| ; SDAG-NEXT: v_sub_i32_e32 v24, vcc, 64, v34 |
| ; SDAG-NEXT: v_lshr_b64 v[22:23], v[4:5], v34 |
| ; SDAG-NEXT: v_lshl_b64 v[24:25], v[6:7], v24 |
| ; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34 |
| ; SDAG-NEXT: v_or_b32_e32 v24, v22, v24 |
| ; SDAG-NEXT: v_subrev_i32_e32 v22, vcc, 64, v34 |
| ; SDAG-NEXT: v_or_b32_e32 v25, v23, v25 |
| ; SDAG-NEXT: v_lshr_b64 v[22:23], v[6:7], v22 |
| ; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v34 |
| ; SDAG-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e64 v27, v23, v5, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v24, vcc |
| ; SDAG-NEXT: v_lshr_b64 v[22:23], v[6:7], v34 |
| ; SDAG-NEXT: v_cndmask_b32_e64 v26, v24, v4, s[4:5] |
| ; SDAG-NEXT: v_cndmask_b32_e32 v31, 0, v23, vcc |
| ; SDAG-NEXT: v_cndmask_b32_e32 v30, 0, v22, vcc |
| ; SDAG-NEXT: v_add_i32_e32 v38, vcc, -1, v12 |
| ; SDAG-NEXT: v_addc_u32_e32 v39, vcc, -1, v13, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v48, vcc, -1, v14, vcc |
| ; SDAG-NEXT: v_addc_u32_e32 v49, vcc, -1, v15, vcc |
| ; SDAG-NEXT: v_mov_b32_e32 v24, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v25, 0 |
| ; SDAG-NEXT: s_mov_b64 s[10:11], 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v28, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v29, 0 |
| ; SDAG-NEXT: v_mov_b32_e32 v23, 0 |
| ; SDAG-NEXT: .LBB5_9: ; %udiv-do-while |
| ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; SDAG-NEXT: v_lshl_b64 v[50:51], v[18:19], 1 |
| ; SDAG-NEXT: v_add_i32_e32 v34, vcc, -1, v34 |
| ; SDAG-NEXT: v_or_b32_e32 v18, v28, v50 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v28, 31, v27 |
| ; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1 |
| ; SDAG-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v19, v29, v51 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v29, 31, v21 |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; SDAG-NEXT: v_addc_u32_e32 v36, vcc, -1, v36, vcc |
| ; SDAG-NEXT: v_lshl_b64 v[30:31], v[30:31], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v26, v26, v29 |
| ; SDAG-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v22 |
| ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, v38, v26 |
| ; SDAG-NEXT: v_or_b32_e32 v30, v30, v28 |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v39, v27, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v48, v30, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v28, v34, v36 |
| ; SDAG-NEXT: v_or_b32_e32 v29, v35, v37 |
| ; SDAG-NEXT: v_subb_u32_e32 v22, vcc, v49, v31, vcc |
| ; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[28:29] |
| ; SDAG-NEXT: v_ashrrev_i32_e32 v28, 31, v22 |
| ; SDAG-NEXT: v_and_b32_e32 v50, v28, v12 |
| ; SDAG-NEXT: v_and_b32_e32 v29, v28, v13 |
| ; SDAG-NEXT: v_sub_i32_e32 v26, vcc, v26, v50 |
| ; SDAG-NEXT: v_subb_u32_e32 v27, vcc, v27, v29, vcc |
| ; SDAG-NEXT: v_and_b32_e32 v51, v28, v14 |
| ; SDAG-NEXT: v_and_b32_e32 v22, 1, v28 |
| ; SDAG-NEXT: v_and_b32_e32 v50, v28, v15 |
| ; SDAG-NEXT: v_subb_u32_e32 v30, vcc, v30, v51, vcc |
| ; SDAG-NEXT: v_or_b32_e32 v21, v25, v21 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v24, v20 |
| ; SDAG-NEXT: s_or_b64 s[10:11], s[4:5], s[10:11] |
| ; SDAG-NEXT: v_mov_b32_e32 v29, v23 |
| ; SDAG-NEXT: v_mov_b32_e32 v28, v22 |
| ; SDAG-NEXT: v_subb_u32_e32 v31, vcc, v31, v50, vcc |
| ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: s_cbranch_execnz .LBB5_9 |
| ; SDAG-NEXT: ; %bb.10: ; %Flow |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] |
| ; SDAG-NEXT: .LBB5_11: ; %Flow11 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 |
| ; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v19 |
| ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 |
| ; SDAG-NEXT: v_or_b32_e32 v20, v20, v24 |
| ; SDAG-NEXT: v_or_b32_e32 v24, v23, v19 |
| ; SDAG-NEXT: v_or_b32_e32 v25, v22, v18 |
| ; SDAG-NEXT: .LBB5_12: ; %Flow12 |
| ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; SDAG-NEXT: v_mul_lo_u32 v11, v33, v11 |
| ; SDAG-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v33, v10, 0 |
| ; SDAG-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v8, v33, 0 |
| ; SDAG-NEXT: v_mul_lo_u32 v22, v32, v10 |
| ; SDAG-NEXT: v_mov_b32_e32 v28, 0 |
| ; SDAG-NEXT: v_add_i32_e32 v19, vcc, v19, v11 |
| ; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v9, v33, v[27:28] |
| ; SDAG-NEXT: v_add_i32_e32 v19, vcc, v19, v22 |
| ; SDAG-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v16, v8, v[18:19] |
| ; SDAG-NEXT: v_mul_lo_u32 v17, v17, v8 |
| ; SDAG-NEXT: v_mov_b32_e32 v27, v10 |
| ; SDAG-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v8, v32, v[27:28] |
| ; SDAG-NEXT: v_mul_lo_u32 v16, v16, v9 |
| ; SDAG-NEXT: v_add_i32_e32 v17, vcc, v17, v19 |
| ; SDAG-NEXT: v_add_i32_e32 v10, vcc, v11, v23 |
| ; SDAG-NEXT: v_addc_u32_e64 v11, s[4:5], 0, 0, vcc |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v9, v32, v[10:11] |
| ; SDAG-NEXT: v_add_i32_e32 v10, vcc, v16, v17 |
| ; SDAG-NEXT: v_mul_lo_u32 v16, v21, v12 |
| ; SDAG-NEXT: v_add_i32_e32 v8, vcc, v8, v18 |
| ; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v26 |
| ; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v22, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v8, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc |
| ; SDAG-NEXT: v_mul_lo_u32 v10, v25, v15 |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v25, v14, 0 |
| ; SDAG-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v12, v25, 0 |
| ; SDAG-NEXT: v_mul_lo_u32 v14, v24, v14 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v9, v10 |
| ; SDAG-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v25, v[27:28] |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v9, v14 |
| ; SDAG-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v20, v12, v[8:9] |
| ; SDAG-NEXT: v_mov_b32_e32 v27, v10 |
| ; SDAG-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v12, v24, v[27:28] |
| ; SDAG-NEXT: v_add_i32_e32 v12, vcc, v16, v9 |
| ; SDAG-NEXT: v_add_i32_e32 v9, vcc, v11, v15 |
| ; SDAG-NEXT: v_mul_lo_u32 v16, v20, v13 |
| ; SDAG-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, vcc |
| ; SDAG-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v24, v[9:10] |
| ; SDAG-NEXT: v_add_i32_e32 v11, vcc, v16, v12 |
| ; SDAG-NEXT: v_add_i32_e32 v8, vcc, v9, v8 |
| ; SDAG-NEXT: v_addc_u32_e32 v9, vcc, v10, v11, vcc |
| ; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v26 |
| ; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v14, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v6, v8, vcc |
| ; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v7, v9, vcc |
| ; SDAG-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GISEL-LABEL: v_urem_v2i128_vv: |
| ; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases |
| ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GISEL-NEXT: v_or_b32_e32 v16, v8, v10 |
| ; GISEL-NEXT: v_or_b32_e32 v17, v9, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] |
| ; GISEL-NEXT: v_or_b32_e32 v16, v0, v2 |
| ; GISEL-NEXT: v_or_b32_e32 v17, v1, v3 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[16:17] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v8 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v16, v9 |
| ; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], 32, v17 |
| ; GISEL-NEXT: v_min_u32_e32 v16, v16, v17 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v10 |
| ; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], 64, v16 |
| ; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], 32, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v11 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[10:11] |
| ; GISEL-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v16, v17, v16, s[6:7] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v1 |
| ; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], 32, v18 |
| ; GISEL-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v19, v2 |
| ; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], 64, v17 |
| ; GISEL-NEXT: v_add_i32_e64 v19, s[6:7], 32, v19 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v3 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[2:3] |
| ; GISEL-NEXT: v_min_u32_e32 v18, v18, v19 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v17, v18, v17, s[6:7] |
| ; GISEL-NEXT: v_sub_i32_e64 v16, s[6:7], v16, v17 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v21, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v17, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_subb_u32_e64 v18, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cmp_gt_u64_e64 s[8:9], v[16:17], v[20:21] |
| ; GISEL-NEXT: v_subb_u32_e64 v19, s[6:7], 0, 0, s[6:7] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_lt_u64_e64 s[8:9], 0, v[18:19] |
| ; GISEL-NEXT: v_xor_b32_e32 v22, 0x7f, v16 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v21, 0, 1, s[8:9] |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[8:9], 0, v[18:19] |
| ; GISEL-NEXT: v_or_b32_e32 v22, v22, v18 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v20, v21, v20, s[8:9] |
| ; GISEL-NEXT: v_or_b32_e32 v23, v17, v19 |
| ; GISEL-NEXT: v_and_b32_e32 v20, 1, v20 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[6:7], 0, v[22:23] |
| ; GISEL-NEXT: v_cmp_ne_u32_e64 s[8:9], 0, v20 |
| ; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] |
| ; GISEL-NEXT: s_mov_b64 s[10:11], exec |
| ; GISEL-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_mov_b64 s[12:13], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e64 v32, v0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v20, v2, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v21, v3, 0, s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[8:9], s[6:7], s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v33, v1, 0, s[4:5] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB5_6 |
| ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 |
| ; GISEL-NEXT: v_add_i32_e32 v29, vcc, 1, v16 |
| ; GISEL-NEXT: v_addc_u32_e32 v30, vcc, 0, v17, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, 0, v18, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, 0, v19, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v20, vcc, 0x7f, v16 |
| ; GISEL-NEXT: v_not_b32_e32 v16, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v23, vcc, v20, v16 |
| ; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v20 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[0:1], v16 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[2:3], v20 |
| ; GISEL-NEXT: v_lshl_b64 v[21:22], v[0:1], v20 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v17, v19 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[0:1], v23 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v21, 0, v21, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v23, v16, v2, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v24, v17, v3, vcc |
| ; GISEL-NEXT: s_mov_b64 s[14:15], s[12:13] |
| ; GISEL-NEXT: v_mov_b32_e32 v17, s13 |
| ; GISEL-NEXT: v_mov_b32_e32 v16, s12 |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s15 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s14 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB5_5 |
| ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 |
| ; GISEL-NEXT: v_sub_i32_e32 v18, vcc, 64, v29 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[0:1], v29 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[2:3], v18 |
| ; GISEL-NEXT: v_add_i32_e32 v20, vcc, 0xffffffc0, v29 |
| ; GISEL-NEXT: v_lshr_b64 v[27:28], v[2:3], v29 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v17, v19 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[2:3], v20 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v29 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v27, 0, v27, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v28, 0, v28, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v33, vcc, -1, v8 |
| ; GISEL-NEXT: v_addc_u32_e32 v34, vcc, -1, v9, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v29 |
| ; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v10, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v25, v16, v0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v26, v17, v1, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v11, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v19, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v20, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v17, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v16, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s10 |
| ; GISEL-NEXT: .LBB5_3: ; %udiv-do-while3 |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[21:22], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v37, 31, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v21, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v22, v17, v19 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[25:26], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v25, 31, v24 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[27:28], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v25 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v27, 31, v26 |
| ; GISEL-NEXT: v_sub_i32_e32 v25, vcc, v33, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v16, v16, v27 |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v34, v19, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v35, v16, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v25, vcc, v36, v17, vcc |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v38, 31, v25 |
| ; GISEL-NEXT: v_and_b32_e32 v25, v38, v8 |
| ; GISEL-NEXT: v_and_b32_e32 v26, v38, v9 |
| ; GISEL-NEXT: v_sub_i32_e32 v25, vcc, v18, v25 |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v19, v26, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v18, v38, v10 |
| ; GISEL-NEXT: v_and_b32_e32 v19, v38, v11 |
| ; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v16, v18, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v28, vcc, v17, v19, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v29, vcc, -1, v29 |
| ; GISEL-NEXT: v_addc_u32_e32 v30, vcc, -1, v30, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v31, vcc, -1, v31, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v32, vcc, -1, v32, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v16, v29, v31 |
| ; GISEL-NEXT: v_or_b32_e32 v17, v30, v32 |
| ; GISEL-NEXT: v_lshl_b64 v[23:24], v[23:24], 1 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] |
| ; GISEL-NEXT: v_and_b32_e32 v19, 1, v38 |
| ; GISEL-NEXT: v_or_b32_e32 v23, v23, v37 |
| ; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v16, v19 |
| ; GISEL-NEXT: v_mov_b32_e32 v17, v20 |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB5_3 |
| ; GISEL-NEXT: ; %bb.4: ; %Flow13 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB5_5: ; %Flow14 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[21:22], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[20:21], v[23:24], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v22, 31, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v20, v20, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v32, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v33, v17, v19 |
| ; GISEL-NEXT: .LBB5_6: ; %Flow16 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_or_b32_e32 v16, v12, v14 |
| ; GISEL-NEXT: v_or_b32_e32 v17, v13, v15 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] |
| ; GISEL-NEXT: v_or_b32_e32 v16, v4, v6 |
| ; GISEL-NEXT: v_or_b32_e32 v17, v5, v7 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[16:17] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v12 |
| ; GISEL-NEXT: s_or_b64 s[10:11], vcc, s[4:5] |
| ; GISEL-NEXT: v_ffbh_u32_e32 v16, v13 |
| ; GISEL-NEXT: v_add_i32_e32 v17, vcc, 32, v17 |
| ; GISEL-NEXT: v_min_u32_e32 v16, v16, v17 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v14 |
| ; GISEL-NEXT: v_add_i32_e32 v16, vcc, 64, v16 |
| ; GISEL-NEXT: v_add_i32_e32 v18, vcc, 32, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v15 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] |
| ; GISEL-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v4 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc |
| ; GISEL-NEXT: v_ffbh_u32_e32 v17, v5 |
| ; GISEL-NEXT: v_add_i32_e32 v18, vcc, 32, v18 |
| ; GISEL-NEXT: v_min_u32_e32 v17, v17, v18 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v19, v6 |
| ; GISEL-NEXT: v_add_i32_e32 v17, vcc, 64, v17 |
| ; GISEL-NEXT: v_add_i32_e32 v19, vcc, 32, v19 |
| ; GISEL-NEXT: v_ffbh_u32_e32 v18, v7 |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] |
| ; GISEL-NEXT: v_min_u32_e32 v18, v18, v19 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc |
| ; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v16, v17 |
| ; GISEL-NEXT: v_subb_u32_e64 v17, s[4:5], 0, 0, vcc |
| ; GISEL-NEXT: v_mov_b32_e32 v18, 0x7f |
| ; GISEL-NEXT: v_mov_b32_e32 v19, 0 |
| ; GISEL-NEXT: v_subb_u32_e64 v22, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[16:17], v[18:19] |
| ; GISEL-NEXT: v_subb_u32_e64 v23, s[4:5], 0, 0, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[22:23] |
| ; GISEL-NEXT: s_mov_b64 s[6:7], exec |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23] |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc |
| ; GISEL-NEXT: v_and_b32_e32 v18, 1, v18 |
| ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 |
| ; GISEL-NEXT: v_xor_b32_e32 v18, 0x7f, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v17, v23 |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[18:19] |
| ; GISEL-NEXT: s_or_b64 s[10:11], s[10:11], vcc |
| ; GISEL-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v24, v4, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v25, v5, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v18, v6, 0, s[10:11] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v19, v7, 0, s[10:11] |
| ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] |
| ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] |
| ; GISEL-NEXT: s_cbranch_execz .LBB5_12 |
| ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 |
| ; GISEL-NEXT: v_add_i32_e32 v34, vcc, 1, v16 |
| ; GISEL-NEXT: v_addc_u32_e32 v35, vcc, 0, v17, vcc |
| ; GISEL-NEXT: v_addc_u32_e32 v36, vcc, 0, v22, vcc |
| ; GISEL-NEXT: s_mov_b64 s[4:5], exec |
| ; GISEL-NEXT: v_addc_u32_e32 v37, vcc, 0, v23, vcc |
| ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, s[4:5] |
| ; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 0x7f, v16 |
| ; GISEL-NEXT: v_not_b32_e32 v16, 63 |
| ; GISEL-NEXT: v_add_i32_e32 v25, vcc, v24, v16 |
| ; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v24 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[4:5], v16 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[6:7], v24 |
| ; GISEL-NEXT: v_lshl_b64 v[22:23], v[4:5], v24 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v17, v19 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[4:5], v25 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v22, 0, v22, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v23, 0, v23, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc |
| ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v24, v16, v6, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v25, v17, v7, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v17, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v16, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s10 |
| ; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] |
| ; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execz .LBB5_11 |
| ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader |
| ; GISEL-NEXT: v_sub_i32_e32 v18, vcc, 64, v34 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[4:5], v34 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[6:7], v18 |
| ; GISEL-NEXT: v_add_i32_e32 v28, vcc, 0xffffffc0, v34 |
| ; GISEL-NEXT: v_lshr_b64 v[26:27], v[6:7], v34 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v19, v17, v19 |
| ; GISEL-NEXT: v_lshr_b64 v[16:17], v[6:7], v28 |
| ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v34 |
| ; GISEL-NEXT: v_cndmask_b32_e32 v16, v16, v18, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v30, 0, v26, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e32 v31, 0, v27, vcc |
| ; GISEL-NEXT: v_add_i32_e32 v38, vcc, -1, v12 |
| ; GISEL-NEXT: v_addc_u32_e32 v39, vcc, -1, v13, vcc |
| ; GISEL-NEXT: s_mov_b64 s[8:9], 0 |
| ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v34 |
| ; GISEL-NEXT: v_addc_u32_e32 v48, vcc, -1, v14, vcc |
| ; GISEL-NEXT: v_cndmask_b32_e64 v28, v16, v4, s[4:5] |
| ; GISEL-NEXT: v_cndmask_b32_e64 v29, v17, v5, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v49, vcc, -1, v15, vcc |
| ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v27, 0 |
| ; GISEL-NEXT: v_mov_b32_e32 v17, s9 |
| ; GISEL-NEXT: v_mov_b32_e32 v16, s8 |
| ; GISEL-NEXT: v_mov_b32_e32 v26, 1 |
| ; GISEL-NEXT: v_mov_b32_e32 v19, s11 |
| ; GISEL-NEXT: v_mov_b32_e32 v18, s10 |
| ; GISEL-NEXT: .LBB5_9: ; %udiv-do-while |
| ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[22:23], 1 |
| ; GISEL-NEXT: v_add_i32_e32 v34, vcc, -1, v34 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v26, 31, v23 |
| ; GISEL-NEXT: v_or_b32_e32 v22, v16, v18 |
| ; GISEL-NEXT: v_or_b32_e32 v23, v17, v19 |
| ; GISEL-NEXT: v_lshl_b64 v[16:17], v[28:29], 1 |
| ; GISEL-NEXT: v_addc_u32_e32 v35, vcc, -1, v35, vcc |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v28, 31, v29 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v29, 31, v25 |
| ; GISEL-NEXT: v_lshl_b64 v[24:25], v[24:25], 1 |
| ; GISEL-NEXT: v_addc_u32_e32 v36, vcc, -1, v36, vcc |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[30:31], 1 |
| ; GISEL-NEXT: v_or_b32_e32 v16, v16, v29 |
| ; GISEL-NEXT: v_addc_u32_e32 v37, vcc, -1, v37, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v24, v24, v26 |
| ; GISEL-NEXT: v_sub_i32_e32 v26, vcc, v38, v16 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v28 |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v39, v17, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v48, v18, vcc |
| ; GISEL-NEXT: v_or_b32_e32 v28, v34, v36 |
| ; GISEL-NEXT: v_or_b32_e32 v29, v35, v37 |
| ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v49, v19, vcc |
| ; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[28:29] |
| ; GISEL-NEXT: v_ashrrev_i32_e32 v28, 31, v26 |
| ; GISEL-NEXT: v_and_b32_e32 v29, v28, v12 |
| ; GISEL-NEXT: v_and_b32_e32 v26, 1, v28 |
| ; GISEL-NEXT: v_and_b32_e32 v30, v28, v13 |
| ; GISEL-NEXT: v_and_b32_e32 v31, v28, v14 |
| ; GISEL-NEXT: v_and_b32_e32 v50, v28, v15 |
| ; GISEL-NEXT: v_sub_i32_e32 v28, vcc, v16, v29 |
| ; GISEL-NEXT: v_subb_u32_e32 v29, vcc, v17, v30, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v30, vcc, v18, v31, vcc |
| ; GISEL-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] |
| ; GISEL-NEXT: v_mov_b32_e32 v16, v26 |
| ; GISEL-NEXT: v_mov_b32_e32 v17, v27 |
| ; GISEL-NEXT: v_subb_u32_e32 v31, vcc, v19, v50, vcc |
| ; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: s_cbranch_execnz .LBB5_9 |
| ; GISEL-NEXT: ; %bb.10: ; %Flow |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] |
| ; GISEL-NEXT: .LBB5_11: ; %Flow11 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] |
| ; GISEL-NEXT: v_lshl_b64 v[26:27], v[22:23], 1 |
| ; GISEL-NEXT: v_lshl_b64 v[18:19], v[24:25], 1 |
| ; GISEL-NEXT: v_lshrrev_b32_e32 v22, 31, v23 |
| ; GISEL-NEXT: v_or_b32_e32 v18, v18, v22 |
| ; GISEL-NEXT: v_or_b32_e32 v24, v16, v26 |
| ; GISEL-NEXT: v_or_b32_e32 v25, v17, v27 |
| ; GISEL-NEXT: .LBB5_12: ; %Flow12 |
| ; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] |
| ; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v8, v20, 0 |
| ; GISEL-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v8, v32, 0 |
| ; GISEL-NEXT: v_mul_lo_u32 v34, v9, v20 |
| ; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v9, v33, v[16:17] |
| ; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v12, v18, 0 |
| ; GISEL-NEXT: v_mad_u64_u32 v[28:29], s[4:5], v10, v32, v[22:23] |
| ; GISEL-NEXT: v_mad_u64_u32 v[30:31], s[4:5], v13, v25, v[16:17] |
| ; GISEL-NEXT: v_mad_u64_u32 v[16:17], vcc, v8, v33, v[27:28] |
| ; GISEL-NEXT: v_mul_lo_u32 v8, v8, v21 |
| ; GISEL-NEXT: v_mad_u64_u32 v[20:21], s[4:5], v12, v24, 0 |
| ; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v14, v24, v[30:31] |
| ; GISEL-NEXT: v_mad_u64_u32 v[27:28], s[4:5], v9, v32, v[16:17] |
| ; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v29, v8, s[4:5] |
| ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v34, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v10, v33, v[8:9] |
| ; GISEL-NEXT: v_mad_u64_u32 v[8:9], vcc, v12, v25, v[21:22] |
| ; GISEL-NEXT: v_mul_lo_u32 v29, v12, v19 |
| ; GISEL-NEXT: v_mul_lo_u32 v30, v13, v18 |
| ; GISEL-NEXT: v_mad_u64_u32 v[18:19], s[4:5], v11, v32, v[16:17] |
| ; GISEL-NEXT: v_mad_u64_u32 v[10:11], s[6:7], v13, v24, v[8:9] |
| ; GISEL-NEXT: v_addc_u32_e64 v8, s[6:7], v23, v29, s[6:7] |
| ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v30, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[12:13], s[6:7], v14, v25, v[8:9] |
| ; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v26 |
| ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], v1, v27, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e64 v2, vcc, v2, v28, s[4:5] |
| ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v18, vcc |
| ; GISEL-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v15, v24, v[12:13] |
| ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v4, v20 |
| ; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v5, v10, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v11, vcc |
| ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v8, vcc |
| ; GISEL-NEXT: s_setpc_b64 s[30:31] |
| %shl = urem <2 x i128> %lhs, %rhs |
| ret <2 x i128> %shl |
| } |
