llvm/test/CodeGen/PowerPC/expand-isel-4.mir

# This file tests the scenario: ISEL R0, ZERO, RX, CR  (X != 0)
# It also tests redundant liveins (%x7) and killed registers.
# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s

--- |
  target datalayout = "E-m:e-i64:64-n32:64"
  target triple = "powerpc64-unknown-linux-gnu"
  define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
  entry:
    %cmp = icmp sgt i32 %i, 0
    %add = add nsw i32 %i, 1
    %cond = select i1 %cmp, i32 %add, i32 %j
    ret i32 %cond
  }

...
---
name:            testExpandISEL
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
liveins:
  - { reg: '%x0' }
  - { reg: '%x3' }
  - { reg: '%x7' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
body:             |
  bb.0.entry:
    liveins: %x0, %x3, %x7

    %r5 = ADDI %r3, 1
    %cr0 = CMPWI %r3, 0
    %r0 = ISEL killed %zero, killed %r5, killed %cr0gt, implicit killed %cr0
    ; CHECK: BC killed %cr0gt, %[[TRUE:bb.[0-9]+]]
    ; CHECK: %[[FALSE:bb.[0-9]+]]
    ; CHECK: %r0 = ORI killed %r5, 0
    ; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
    ; CHECK: [[TRUE]]
    ; CHECK: %r0 = ADDI killed %zero, 0

    %x0 = EXTSW_32_64 killed %r0

...