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llvm / llvm-project / dd0161f6025bb97f6784e0bc7e1b5849acae44dd
commitdd0161f6025bb97f6784e0bc7e1b5849acae44dd[log] [tgz]
authorDavid Sherwood <david.sherwood@arm.com>Mon Sep 08 10:34:53 2025 +0100
committerGitHub <noreply@github.com>Mon Sep 08 10:34:53 2025 +0100
tree3fdad8b966be3429cef4aa7a2a8ab2c4dda63483
parentc71da7d5e0f63e7158c1260dfac034896150b669 [diff]
[AArch64] Improve lowering for scalable masked interleaving stores (#156718)

Similar to #154338, this PR aims to support lowering of certain IR
to SVE's st2 and st4 instructions. The typical IR scenario looks
like:

%mask = .. @llvm.vector.interleave2(<vscale x 16 x i1> %m, <vscale x 16
x i1> %m)
%val = .. @llvm.vector.interleave2(<vscale x 16 x i8> %v1, <vscale x 16
x i8> %v2)
.. @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %val, ..., <vscale x
32 x i1> %mask)

where we're interleaving both the value and the mask being passed
to the wide store. When the mask interleave parts are identical
we can lower this to st2b.

This PR adds a DAG combine for lowering this kind of IR pattern
to st2X and st4X SVE instructions.
4 files changed
tree: 3fdad8b966be3429cef4aa7a2a8ab2c4dda63483
  1. .ci/
  2. .github/
  3. bolt/
  4. clang/
  5. clang-tools-extra/
  6. cmake/
  7. compiler-rt/
  8. cross-project-tests/
  9. flang/
  10. flang-rt/
  11. libc/
  12. libclc/
  13. libcxx/
  14. libcxxabi/
  15. libsycl/
  16. libunwind/
  17. lld/
  18. lldb/
  19. llvm/
  20. llvm-libgcc/
  21. mlir/
  22. offload/
  23. openmp/
  24. orc-rt/
  25. polly/
  26. runtimes/
  27. third-party/
  28. utils/
  29. .clang-format
  30. .clang-format-ignore
  31. .clang-tidy
  32. .git-blame-ignore-revs
  33. .gitattributes
  34. .gitignore
  35. .mailmap
  36. CODE_OF_CONDUCT.md
  37. CONTRIBUTING.md
  38. LICENSE.TXT
  39. pyproject.toml
  40. README.md
  41. SECURITY.md
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