)]}'
{
  "commit": "dd0161f6025bb97f6784e0bc7e1b5849acae44dd",
  "tree": "3fdad8b966be3429cef4aa7a2a8ab2c4dda63483",
  "parents": [
    "c71da7d5e0f63e7158c1260dfac034896150b669"
  ],
  "author": {
    "name": "David Sherwood",
    "email": "david.sherwood@arm.com",
    "time": "Mon Sep 08 10:34:53 2025 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Sep 08 10:34:53 2025 +0100"
  },
  "message": "[AArch64] Improve lowering for scalable masked interleaving stores (#156718)\n\nSimilar to #154338, this PR aims to support lowering of certain IR\nto SVE\u0027s st2 and st4 instructions. The typical IR scenario looks\nlike:\n\n%mask \u003d .. @llvm.vector.interleave2(\u003cvscale x 16 x i1\u003e %m, \u003cvscale x 16\nx i1\u003e %m)\n%val \u003d .. @llvm.vector.interleave2(\u003cvscale x 16 x i8\u003e %v1, \u003cvscale x 16\nx i8\u003e %v2)\n.. @llvm.masked.store.nxv32i8.p0(\u003cvscale x 32 x i8\u003e %val, ..., \u003cvscale x\n32 x i1\u003e %mask)\n\nwhere we\u0027re interleaving both the value and the mask being passed\nto the wide store. When the mask interleave parts are identical\nwe can lower this to st2b.\n\nThis PR adds a DAG combine for lowering this kind of IR pattern\nto st2X and st4X SVE instructions.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4248b0144ef18c5e9495843d281dff6300293f80",
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      "old_path": "llvm/include/llvm/CodeGen/SelectionDAGNodes.h",
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      "new_mode": 33188,
      "new_path": "llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp"
    },
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      "new_id": "ac1db2bc56bbd067400befe5df458022c825fac0",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AArch64/fixed_masked_interleaved_stores.ll"
    },
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      "new_path": "llvm/test/CodeGen/AArch64/scalable_masked_interleaved_stores.ll"
    }
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}