| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s |
| |
| define void @test(ptr %p, i64 %a, i8 %b) { |
| ; CHECK-LABEL: define void @test( |
| ; CHECK-SAME: ptr [[P:%.*]], i64 [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br i1 false, label [[SCALAR_PH1:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[B]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i64> poison, i64 [[A]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i64> [[BROADCAST_SPLATINSERT1]], <16 x i64> poison, <16 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP0:%.*]] = shl <16 x i64> [[BROADCAST_SPLAT2]], splat (i64 48) |
| ; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i64> [[TMP0]], splat (i64 52) |
| ; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i64> [[TMP1]] to <16 x i32> |
| ; CHECK-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[BROADCAST_SPLAT]] to <16 x i32> |
| ; CHECK-NEXT: br label [[FOR_COND:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ] |
| ; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 9) |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <16 x i32> [[VEC_IND]], splat (i32 2) |
| ; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i1> [[TMP4]], <16 x i1> zeroinitializer |
| ; CHECK-NEXT: [[PREDPHI:%.*]] = select <16 x i1> [[TMP5]], <16 x i32> [[TMP3]], <16 x i32> [[TMP2]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = shl <16 x i32> [[PREDPHI]], splat (i32 8) |
| ; CHECK-NEXT: [[TMP8:%.*]] = trunc <16 x i32> [[TMP6]] to <16 x i8> |
| ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 0 |
| ; CHECK-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF:%.*]], label [[VECTOR_BODY:%.*]] |
| ; CHECK: pred.store.if: |
| ; CHECK-NEXT: [[TMP19:%.*]] = extractelement <16 x i8> [[TMP8]], i32 0 |
| ; CHECK-NEXT: store i8 [[TMP19]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[VECTOR_BODY]] |
| ; CHECK: pred.store.continue: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 1 |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH:%.*]] |
| ; CHECK: pred.store.if3: |
| ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <16 x i8> [[TMP8]], i32 1 |
| ; CHECK-NEXT: store i8 [[TMP12]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: pred.store.continue4: |
| ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 2 |
| ; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]] |
| ; CHECK: pred.store.if5: |
| ; CHECK-NEXT: [[TMP14:%.*]] = extractelement <16 x i8> [[TMP8]], i32 2 |
| ; CHECK-NEXT: store i8 [[TMP14]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] |
| ; CHECK: pred.store.continue6: |
| ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 3 |
| ; CHECK-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE9:%.*]] |
| ; CHECK: pred.store.if7: |
| ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <16 x i8> [[TMP8]], i32 3 |
| ; CHECK-NEXT: store i8 [[TMP16]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE9]] |
| ; CHECK: pred.store.continue8: |
| ; CHECK-NEXT: [[TMP17:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 4 |
| ; CHECK-NEXT: br i1 [[TMP17]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]] |
| ; CHECK: pred.store.if9: |
| ; CHECK-NEXT: [[TMP18:%.*]] = extractelement <16 x i8> [[TMP8]], i32 4 |
| ; CHECK-NEXT: store i8 [[TMP18]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]] |
| ; CHECK: pred.store.continue10: |
| ; CHECK-NEXT: [[TMP41:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 5 |
| ; CHECK-NEXT: br i1 [[TMP41]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]] |
| ; CHECK: pred.store.if11: |
| ; CHECK-NEXT: [[TMP20:%.*]] = extractelement <16 x i8> [[TMP8]], i32 5 |
| ; CHECK-NEXT: store i8 [[TMP20]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE12]] |
| ; CHECK: pred.store.continue12: |
| ; CHECK-NEXT: [[TMP21:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 6 |
| ; CHECK-NEXT: br i1 [[TMP21]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14:%.*]] |
| ; CHECK: pred.store.if13: |
| ; CHECK-NEXT: [[TMP22:%.*]] = extractelement <16 x i8> [[TMP8]], i32 6 |
| ; CHECK-NEXT: store i8 [[TMP22]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE14]] |
| ; CHECK: pred.store.continue14: |
| ; CHECK-NEXT: [[TMP23:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 7 |
| ; CHECK-NEXT: br i1 [[TMP23]], label [[PRED_STORE_IF15:%.*]], label [[PRED_STORE_CONTINUE16:%.*]] |
| ; CHECK: pred.store.if15: |
| ; CHECK-NEXT: [[TMP24:%.*]] = extractelement <16 x i8> [[TMP8]], i32 7 |
| ; CHECK-NEXT: store i8 [[TMP24]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE16]] |
| ; CHECK: pred.store.continue16: |
| ; CHECK-NEXT: [[TMP25:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 8 |
| ; CHECK-NEXT: br i1 [[TMP25]], label [[PRED_STORE_IF17:%.*]], label [[PRED_STORE_CONTINUE18:%.*]] |
| ; CHECK: pred.store.if17: |
| ; CHECK-NEXT: [[TMP26:%.*]] = extractelement <16 x i8> [[TMP8]], i32 8 |
| ; CHECK-NEXT: store i8 [[TMP26]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE18]] |
| ; CHECK: pred.store.continue18: |
| ; CHECK-NEXT: [[TMP27:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 9 |
| ; CHECK-NEXT: br i1 [[TMP27]], label [[PRED_STORE_IF19:%.*]], label [[PRED_STORE_CONTINUE20:%.*]] |
| ; CHECK: pred.store.if19: |
| ; CHECK-NEXT: [[TMP28:%.*]] = extractelement <16 x i8> [[TMP8]], i32 9 |
| ; CHECK-NEXT: store i8 [[TMP28]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE20]] |
| ; CHECK: pred.store.continue20: |
| ; CHECK-NEXT: [[TMP29:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 10 |
| ; CHECK-NEXT: br i1 [[TMP29]], label [[PRED_STORE_IF21:%.*]], label [[PRED_STORE_CONTINUE22:%.*]] |
| ; CHECK: pred.store.if21: |
| ; CHECK-NEXT: [[TMP30:%.*]] = extractelement <16 x i8> [[TMP8]], i32 10 |
| ; CHECK-NEXT: store i8 [[TMP30]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE22]] |
| ; CHECK: pred.store.continue22: |
| ; CHECK-NEXT: [[TMP31:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 11 |
| ; CHECK-NEXT: br i1 [[TMP31]], label [[PRED_STORE_IF23:%.*]], label [[PRED_STORE_CONTINUE24:%.*]] |
| ; CHECK: pred.store.if23: |
| ; CHECK-NEXT: [[TMP32:%.*]] = extractelement <16 x i8> [[TMP8]], i32 11 |
| ; CHECK-NEXT: store i8 [[TMP32]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE24]] |
| ; CHECK: pred.store.continue24: |
| ; CHECK-NEXT: [[TMP33:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 12 |
| ; CHECK-NEXT: br i1 [[TMP33]], label [[PRED_STORE_IF25:%.*]], label [[PRED_STORE_CONTINUE26:%.*]] |
| ; CHECK: pred.store.if25: |
| ; CHECK-NEXT: [[TMP34:%.*]] = extractelement <16 x i8> [[TMP8]], i32 12 |
| ; CHECK-NEXT: store i8 [[TMP34]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE26]] |
| ; CHECK: pred.store.continue26: |
| ; CHECK-NEXT: [[TMP35:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 13 |
| ; CHECK-NEXT: br i1 [[TMP35]], label [[PRED_STORE_IF27:%.*]], label [[PRED_STORE_CONTINUE28:%.*]] |
| ; CHECK: pred.store.if27: |
| ; CHECK-NEXT: [[TMP36:%.*]] = extractelement <16 x i8> [[TMP8]], i32 13 |
| ; CHECK-NEXT: store i8 [[TMP36]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE28]] |
| ; CHECK: pred.store.continue28: |
| ; CHECK-NEXT: [[TMP37:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 14 |
| ; CHECK-NEXT: br i1 [[TMP37]], label [[PRED_STORE_IF29:%.*]], label [[PRED_STORE_CONTINUE30:%.*]] |
| ; CHECK: pred.store.if29: |
| ; CHECK-NEXT: [[TMP38:%.*]] = extractelement <16 x i8> [[TMP8]], i32 14 |
| ; CHECK-NEXT: store i8 [[TMP38]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE30]] |
| ; CHECK: pred.store.continue30: |
| ; CHECK-NEXT: [[TMP39:%.*]] = extractelement <16 x i1> [[ACTIVE_LANE_MASK]], i32 15 |
| ; CHECK-NEXT: br i1 [[TMP39]], label [[PRED_STORE_IF31:%.*]], label [[PRED_STORE_CONTINUE8]] |
| ; CHECK: pred.store.if31: |
| ; CHECK-NEXT: [[TMP40:%.*]] = extractelement <16 x i8> [[TMP8]], i32 15 |
| ; CHECK-NEXT: store i8 [[TMP40]], ptr [[P]], align 1 |
| ; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]] |
| ; CHECK: pred.store.continue32: |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <16 x i32> [[VEC_IND]], splat (i32 16) |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16 |
| ; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[FOR_COND]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br i1 true, label [[EXIT1:%.*]], label [[SCALAR_PH1]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 16, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: br label [[FOR_COND1:%.*]] |
| ; CHECK: for.cond: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH1]] ], [ [[ADD:%.*]], [[FOR_BODY:%.*]] ] |
| ; CHECK-NEXT: [[ADD]] = add i32 [[IV]], 1 |
| ; CHECK-NEXT: [[CMP_SLT:%.*]] = icmp slt i32 [[IV]], 2 |
| ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], 48 |
| ; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[SHL]], 52 |
| ; CHECK-NEXT: [[TRUNC_I32:%.*]] = trunc i64 [[ASHR]] to i32 |
| ; CHECK-NEXT: br i1 [[CMP_SLT]], label [[COND_FALSE:%.*]], label [[FOR_BODY]] |
| ; CHECK: cond.false: |
| ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[B]] to i32 |
| ; CHECK-NEXT: br label [[FOR_BODY]] |
| ; CHECK: for.body: |
| ; CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TRUNC_I32]], [[FOR_COND1]] ], [ [[ZEXT]], [[COND_FALSE]] ] |
| ; CHECK-NEXT: [[SHL_I32:%.*]] = shl i32 [[COND]], 8 |
| ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL_I32]] to i8 |
| ; CHECK-NEXT: store i8 [[TRUNC]], ptr [[P]], align 1 |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[IV]], 8 |
| ; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND1]], label [[EXIT1]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %for.cond |
| |
| for.cond: ; preds = %for.body, %entry |
| %iv = phi i32 [ 0, %entry ], [ %add, %for.body ] |
| %add = add i32 %iv, 1 |
| %cmp.slt = icmp slt i32 %iv, 2 |
| %shl = shl i64 %a, 48 |
| %ashr = ashr i64 %shl, 52 |
| %trunc.i32 = trunc i64 %ashr to i32 |
| br i1 %cmp.slt, label %cond.false, label %for.body |
| |
| cond.false: ; preds = %for.cond |
| %zext = zext i8 %b to i32 |
| br label %for.body |
| |
| for.body: ; preds = %cond.false, %for.cond |
| %cond = phi i32 [ %trunc.i32, %for.cond ], [ %zext, %cond.false ] |
| %shl.i32 = shl i32 %cond, 8 |
| %trunc = trunc i32 %shl.i32 to i8 |
| store i8 %trunc, ptr %p, align 1 |
| %cmp = icmp slt i32 %iv, 8 |
| br i1 %cmp, label %for.cond, label %exit |
| |
| exit: ; preds = %for.body |
| ret void |
| } |
| ;. |
| ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} |
| ;. |
