llvm/test/CodeGen/AMDGPU/livevars-implicitdef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn --run-pass=livevars -o - %s | FileCheck %s
---
# Check that super register is defined for an sgpr copy.
name:            sgpr_copy
tracksRegLiveness: true
body:             |
  bb.0:

    ; CHECK-LABEL: name: sgpr_copy
    ; CHECK: %sval:sreg_32 = S_MOV_B32 0
    ; CHECK-NEXT: $sgpr0 = COPY %sval
    ; CHECK-NEXT: $sgpr1 = COPY %sval
    ; CHECK-NEXT: $sgpr2 = COPY %sval
    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
    %sval:sreg_32 = S_MOV_B32 0

    $sgpr0 = COPY %sval
    $sgpr1 = COPY %sval
    $sgpr2 = COPY %sval
    $sgpr3 = COPY %sval
    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3

...
---
# Check that super register is defined for a vgpr vector copy.
name:            vgpr_copy
tracksRegLiveness: true
body:             |
  bb.0:

    ; CHECK-LABEL: name: vgpr_copy
    ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK-NEXT: $vgpr0 = COPY %vval
    ; CHECK-NEXT: $vgpr1 = COPY %vval
    ; CHECK-NEXT: $vgpr2 = COPY %vval
    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
    %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    $vgpr0 = COPY %vval
    $vgpr1 = COPY %vval
    $vgpr2 = COPY %vval
    $vgpr3 = COPY %vval
    %0:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3

...
---
# Check that super register is defined when there is a hole.
name:            sgpr_copy_hole
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: sgpr_copy_hole
    ; CHECK: %sval:sreg_32 = S_MOV_B32 0
    ; CHECK-NEXT: $sgpr0 = COPY %sval
    ; CHECK-NEXT: $sgpr2 = COPY %sval
    ; CHECK-NEXT: $sgpr3 = COPY killed %sval
    ; CHECK-NEXT: SI_RETURN implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
    %sval:sreg_32 = S_MOV_B32 0

    $sgpr0 = COPY %sval
    $sgpr2 = COPY %sval
    $sgpr3 = COPY %sval
    SI_RETURN implicit $sgpr0_sgpr1_sgpr2_sgpr3

...
---
# Check that super register is defined when a pair interrupts the sequence.
name:            vgpr_copy_pair
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: vgpr_copy_pair
    ; CHECK: %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK-NEXT: $vgpr0 = COPY %vval
    ; CHECK-NEXT: $vgpr1 = COPY %vval
    ; CHECK-NEXT: $vgpr2 = COPY %vval
    ; CHECK-NEXT: $vgpr3 = COPY killed %vval
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1_vgpr2
    ; CHECK-NEXT: dead [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0_vgpr1_vgpr2_vgpr3
    %vval:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    $vgpr0 = COPY %vval
    $vgpr1 = COPY %vval
    $vgpr2 = COPY %vval
    $vgpr3 = COPY %vval
    %0:vgpr_32 = COPY $vgpr1_vgpr2
    %1:vgpr_32 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
...