llvm/test/CodeGen/AMDGPU/fold-multiple-commute.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck %s

# Check that the addc instructions are commuted to allow folding of the constant
# 0 into multiple uses as an inline operand.
---
name: test_commute
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vcc
    ; CHECK-LABEL: name: test_commute
    ; CHECK: liveins: $vgpr0, $vgpr1, $vcc
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY]], implicit-def $vcc, implicit $vcc, implicit $exec
    ; CHECK-NEXT: [[V_ADDC_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY1]], implicit-def $vcc, implicit $vcc, implicit $exec
    ; CHECK-NEXT: S_NOP 0, implicit [[V_ADDC_U32_e32_]], implicit [[V_ADDC_U32_e32_1]]
    %0:vgpr_32 = COPY $vgpr0
    %1:vgpr_32 = COPY $vgpr1
    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %3:vgpr_32 = V_ADDC_U32_e32 %0, %2, implicit-def $vcc, implicit $vcc, implicit $exec
    %4:vgpr_32 = V_ADDC_U32_e32 %1, %2, implicit-def $vcc, implicit $vcc, implicit $exec
    S_NOP 0, implicit %3, implicit %4
...