llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX8 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX11 %s

define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_offset(ptr addrspace(1) %out, [8 x i32], ptr addrspace(3) %ptr, [8 x i32], i32 %swap) nounwind {
; CHECK-LABEL: lds_atomic_cmpxchg_ret_i32_offset:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dword s2, s[4:5], 0x13
; CHECK-NEXT:    s_load_dword s3, s[4:5], 0x1c
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; CHECK-NEXT:    v_mov_b32_e32 v0, 7
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v1, s2
; CHECK-NEXT:    v_mov_b32_e32 v2, s3
; CHECK-NEXT:    s_mov_b32 m0, -1
; CHECK-NEXT:    ds_cmpst_rtn_b32 v0, v1, v0, v2 offset:16
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s3, 0xf000
; CHECK-NEXT:    s_mov_b32 s2, -1
; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; CHECK-NEXT:    s_endpgm
;
; GFX7-LABEL: lds_atomic_cmpxchg_ret_i32_offset:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dword s2, s[4:5], 0x13
; GFX7-NEXT:    s_load_dword s3, s[4:5], 0x1c
; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-NEXT:    v_mov_b32_e32 v0, 7
; GFX7-NEXT:    s_mov_b32 m0, -1
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v1, s2
; GFX7-NEXT:    v_mov_b32_e32 v2, s3
; GFX7-NEXT:    ds_cmpst_rtn_b32 v0, v1, v0, v2 offset:16
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: lds_atomic_cmpxchg_ret_i32_offset:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s2, s[4:5], 0x4c
; GFX8-NEXT:    s_load_dword s3, s[4:5], 0x70
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    v_mov_b32_e32 v0, 7
; GFX8-NEXT:    s_mov_b32 m0, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v1, s2
; GFX8-NEXT:    v_mov_b32_e32 v2, s3
; GFX8-NEXT:    ds_cmpst_rtn_b32 v2, v1, v0, v2 offset:16
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    flat_store_dword v[0:1], v2
; GFX8-NEXT:    s_endpgm
;
; GFX9-LABEL: lds_atomic_cmpxchg_ret_i32_offset:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x4c
; GFX9-NEXT:    s_load_dword s3, s[4:5], 0x70
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT:    v_mov_b32_e32 v0, 7
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_mov_b32_e32 v2, s3
; GFX9-NEXT:    ds_cmpst_rtn_b32 v0, v1, v0, v2 offset:16
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
; GFX9-NEXT:    s_endpgm
;
; GFX11-LABEL: lds_atomic_cmpxchg_ret_i32_offset:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    s_load_b32 s0, s[4:5], 0x4c
; GFX11-NEXT:    s_load_b32 s1, s[4:5], 0x70
; GFX11-NEXT:    v_mov_b32_e32 v0, 7
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v1, s0
; GFX11-NEXT:    v_mov_b32_e32 v2, s1
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    ds_cmpstore_rtn_b32 v0, v1, v2, v0 offset:16
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    buffer_gl0_inv
; GFX11-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT:    s_endpgm
  %gep = getelementptr i32, ptr addrspace(3) %ptr, i32 4
  %pair = cmpxchg ptr addrspace(3) %gep, i32 7, i32 %swap seq_cst monotonic
  %result = extractvalue { i32, i1 } %pair, 0
  store i32 %result, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i64_offset(ptr addrspace(1) %out, ptr addrspace(3) %ptr, i64 %swap) nounwind {
; CHECK-LABEL: lds_atomic_cmpxchg_ret_i64_offset:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dword s6, s[4:5], 0xb
; CHECK-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0xd
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; CHECK-NEXT:    v_mov_b32_e32 v0, 7
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v4, s6
; CHECK-NEXT:    v_mov_b32_e32 v2, s2
; CHECK-NEXT:    v_mov_b32_e32 v3, s3
; CHECK-NEXT:    s_mov_b32 m0, -1
; CHECK-NEXT:    ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3] offset:32
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s3, 0xf000
; CHECK-NEXT:    s_mov_b32 s2, -1
; CHECK-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; CHECK-NEXT:    s_endpgm
;
; GFX7-LABEL: lds_atomic_cmpxchg_ret_i64_offset:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dword s6, s[4:5], 0xb
; GFX7-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0xd
; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-NEXT:    v_mov_b32_e32 v0, 7
; GFX7-NEXT:    v_mov_b32_e32 v1, 0
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v4, s6
; GFX7-NEXT:    v_mov_b32_e32 v2, s2
; GFX7-NEXT:    v_mov_b32_e32 v3, s3
; GFX7-NEXT:    s_mov_b32 m0, -1
; GFX7-NEXT:    ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3] offset:32
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: lds_atomic_cmpxchg_ret_i64_offset:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX8-NEXT:    v_mov_b32_e32 v0, 7
; GFX8-NEXT:    v_mov_b32_e32 v1, 0
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v4, s6
; GFX8-NEXT:    v_mov_b32_e32 v3, s1
; GFX8-NEXT:    v_mov_b32_e32 v2, s0
; GFX8-NEXT:    s_mov_b32 m0, -1
; GFX8-NEXT:    ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3] offset:32
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v2, s2
; GFX8-NEXT:    v_mov_b32_e32 v3, s3
; GFX8-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT:    s_endpgm
;
; GFX9-LABEL: lds_atomic_cmpxchg_ret_i64_offset:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-NEXT:    v_mov_b32_e32 v0, 7
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v4, s6
; GFX9-NEXT:    v_mov_b32_e32 v3, s1
; GFX9-NEXT:    v_mov_b32_e32 v2, s0
; GFX9-NEXT:    ds_cmpst_rtn_b64 v[0:1], v4, v[0:1], v[2:3] offset:32
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT:    s_endpgm
;
; GFX11-LABEL: lds_atomic_cmpxchg_ret_i64_offset:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
; GFX11-NEXT:    v_mov_b32_e32 v0, 7
; GFX11-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-NEXT:    v_mov_b32_e32 v3, s1
; GFX11-NEXT:    v_mov_b32_e32 v2, s0
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    ds_cmpstore_rtn_b64 v[0:1], v4, v[2:3], v[0:1] offset:32
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    buffer_gl0_inv
; GFX11-NEXT:    v_mov_b32_e32 v2, 0
; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT:    s_endpgm
  %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4
  %pair = cmpxchg ptr addrspace(3) %gep, i64 7, i64 %swap seq_cst monotonic
  %result = extractvalue { i64, i1 } %pair, 0
  store i64 %result, ptr addrspace(1) %out, align 8
  ret void
}

define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(ptr addrspace(1) %out, ptr addrspace(3) %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: lds_atomic_cmpxchg_ret_i32_bad_si_offset:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xc
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_load_dword s3, s[4:5], 0xb
; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9
; CHECK-NEXT:    s_sub_i32 s1, s1, s2
; CHECK-NEXT:    s_lshl_b32 s1, s1, 2
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_add_i32 s1, s3, s1
; CHECK-NEXT:    s_add_i32 s1, s1, 16
; CHECK-NEXT:    v_mov_b32_e32 v0, 7
; CHECK-NEXT:    v_mov_b32_e32 v1, s0
; CHECK-NEXT:    v_mov_b32_e32 v2, s1
; CHECK-NEXT:    s_mov_b32 m0, -1
; CHECK-NEXT:    ds_cmpst_rtn_b32 v0, v2, v0, v1
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_mov_b32 s7, 0xf000
; CHECK-NEXT:    s_mov_b32 s6, -1
; CHECK-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; CHECK-NEXT:    s_endpgm
;
; GFX7-LABEL: lds_atomic_cmpxchg_ret_i32_bad_si_offset:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-NEXT:    v_mov_b32_e32 v0, 7
; GFX7-NEXT:    s_mov_b32 m0, -1
; GFX7-NEXT:    s_mov_b32 s7, 0xf000
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_sub_i32 s2, s2, s3
; GFX7-NEXT:    v_mov_b32_e32 v1, s1
; GFX7-NEXT:    s_lshl_b32 s1, s2, 2
; GFX7-NEXT:    s_add_i32 s0, s0, s1
; GFX7-NEXT:    v_mov_b32_e32 v2, s0
; GFX7-NEXT:    ds_cmpst_rtn_b32 v0, v2, v0, v1 offset:16
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_mov_b32 s6, -1
; GFX7-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: lds_atomic_cmpxchg_ret_i32_bad_si_offset:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x24
; GFX8-NEXT:    v_mov_b32_e32 v0, 7
; GFX8-NEXT:    s_mov_b32 m0, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_sub_i32 s2, s2, s3
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    s_lshl_b32 s1, s2, 2
; GFX8-NEXT:    s_add_i32 s0, s0, s1
; GFX8-NEXT:    v_mov_b32_e32 v2, s0
; GFX8-NEXT:    ds_cmpst_rtn_b32 v2, v2, v0, v1 offset:16
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v0, s4
; GFX8-NEXT:    v_mov_b32_e32 v1, s5
; GFX8-NEXT:    flat_store_dword v[0:1], v2
; GFX8-NEXT:    s_endpgm
;
; GFX9-LABEL: lds_atomic_cmpxchg_ret_i32_bad_si_offset:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT:    v_mov_b32_e32 v0, 7
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_sub_i32 s2, s2, s3
; GFX9-NEXT:    s_lshl_b32 s2, s2, 2
; GFX9-NEXT:    s_add_i32 s0, s0, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s1
; GFX9-NEXT:    ds_cmpst_rtn_b32 v0, v1, v0, v2 offset:16
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    global_store_dword v1, v0, s[6:7]
; GFX9-NEXT:    s_endpgm
;
; GFX11-LABEL: lds_atomic_cmpxchg_ret_i32_bad_si_offset:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT:    v_mov_b32_e32 v0, 7
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    s_sub_i32 s2, s2, s3
; GFX11-NEXT:    v_mov_b32_e32 v2, s1
; GFX11-NEXT:    s_lshl_b32 s2, s2, 2
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT:    s_add_i32 s0, s0, s2
; GFX11-NEXT:    v_mov_b32_e32 v1, s0
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    ds_cmpstore_rtn_b32 v0, v1, v2, v0 offset:16
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    buffer_gl0_inv
; GFX11-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT:    s_endpgm
  %sub = sub i32 %a, %b
  %add = add i32 %sub, 4
  %gep = getelementptr i32, ptr addrspace(3) %ptr, i32 %add
  %pair = cmpxchg ptr addrspace(3) %gep, i32 7, i32 %swap seq_cst monotonic
  %result = extractvalue { i32, i1 } %pair, 0
  store i32 %result, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i32_offset(ptr addrspace(3) %ptr, [8 x i32], i32 %swap) nounwind {
; CHECK-LABEL: lds_atomic_cmpxchg_noret_i32_offset:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dword s0, s[4:5], 0x9
; CHECK-NEXT:    s_load_dword s1, s[4:5], 0x12
; CHECK-NEXT:    v_mov_b32_e32 v0, 7
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v1, s0
; CHECK-NEXT:    v_mov_b32_e32 v2, s1
; CHECK-NEXT:    s_mov_b32 m0, -1
; CHECK-NEXT:    ds_cmpst_b32 v1, v0, v2 offset:16
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_endpgm
;
; GFX7-LABEL: lds_atomic_cmpxchg_noret_i32_offset:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dword s0, s[4:5], 0x9
; GFX7-NEXT:    s_load_dword s1, s[4:5], 0x12
; GFX7-NEXT:    v_mov_b32_e32 v0, 7
; GFX7-NEXT:    s_mov_b32 m0, -1
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v1, s0
; GFX7-NEXT:    v_mov_b32_e32 v2, s1
; GFX7-NEXT:    ds_cmpst_b32 v1, v0, v2 offset:16
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: lds_atomic_cmpxchg_noret_i32_offset:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s0, s[4:5], 0x24
; GFX8-NEXT:    s_load_dword s1, s[4:5], 0x48
; GFX8-NEXT:    v_mov_b32_e32 v0, 7
; GFX8-NEXT:    s_mov_b32 m0, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v1, s0
; GFX8-NEXT:    v_mov_b32_e32 v2, s1
; GFX8-NEXT:    ds_cmpst_b32 v1, v0, v2 offset:16
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_endpgm
;
; GFX9-LABEL: lds_atomic_cmpxchg_noret_i32_offset:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s0, s[4:5], 0x24
; GFX9-NEXT:    s_load_dword s1, s[4:5], 0x48
; GFX9-NEXT:    v_mov_b32_e32 v0, 7
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v1, s0
; GFX9-NEXT:    v_mov_b32_e32 v2, s1
; GFX9-NEXT:    ds_cmpst_b32 v1, v0, v2 offset:16
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_endpgm
;
; GFX11-LABEL: lds_atomic_cmpxchg_noret_i32_offset:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    s_load_b32 s0, s[4:5], 0x24
; GFX11-NEXT:    s_load_b32 s1, s[4:5], 0x48
; GFX11-NEXT:    v_mov_b32_e32 v0, 7
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v1, s0
; GFX11-NEXT:    v_mov_b32_e32 v2, s1
; GFX11-NEXT:    ds_cmpstore_b32 v1, v2, v0 offset:16
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    buffer_gl0_inv
; GFX11-NEXT:    s_endpgm
  %gep = getelementptr i32, ptr addrspace(3) %ptr, i32 4
  %pair = cmpxchg ptr addrspace(3) %gep, i32 7, i32 %swap seq_cst monotonic
  %result = extractvalue { i32, i1 } %pair, 0
  ret void
}

define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i64_offset(ptr addrspace(3) %ptr, i64 %swap) nounwind {
; CHECK-LABEL: lds_atomic_cmpxchg_noret_i64_offset:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_load_dword s2, s[4:5], 0x9
; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xb
; CHECK-NEXT:    v_mov_b32_e32 v0, 7
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v4, s2
; CHECK-NEXT:    v_mov_b32_e32 v3, s1
; CHECK-NEXT:    v_mov_b32_e32 v2, s0
; CHECK-NEXT:    s_mov_b32 m0, -1
; CHECK-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] offset:32
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_endpgm
;
; GFX7-LABEL: lds_atomic_cmpxchg_noret_i64_offset:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dword s2, s[4:5], 0x9
; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xb
; GFX7-NEXT:    v_mov_b32_e32 v0, 7
; GFX7-NEXT:    v_mov_b32_e32 v1, 0
; GFX7-NEXT:    s_mov_b32 m0, -1
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v4, s2
; GFX7-NEXT:    v_mov_b32_e32 v3, s1
; GFX7-NEXT:    v_mov_b32_e32 v2, s0
; GFX7-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] offset:32
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: lds_atomic_cmpxchg_noret_i64_offset:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s2, s[4:5], 0x24
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX8-NEXT:    v_mov_b32_e32 v0, 7
; GFX8-NEXT:    v_mov_b32_e32 v1, 0
; GFX8-NEXT:    s_mov_b32 m0, -1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v4, s2
; GFX8-NEXT:    v_mov_b32_e32 v3, s1
; GFX8-NEXT:    v_mov_b32_e32 v2, s0
; GFX8-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] offset:32
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    s_endpgm
;
; GFX9-LABEL: lds_atomic_cmpxchg_noret_i64_offset:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x24
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2c
; GFX9-NEXT:    v_mov_b32_e32 v0, 7
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v4, s2
; GFX9-NEXT:    v_mov_b32_e32 v3, s1
; GFX9-NEXT:    v_mov_b32_e32 v2, s0
; GFX9-NEXT:    ds_cmpst_b64 v4, v[0:1], v[2:3] offset:32
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_endpgm
;
; GFX11-LABEL: lds_atomic_cmpxchg_noret_i64_offset:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_clause 0x1
; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x24
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-NEXT:    v_mov_b32_e32 v0, 7
; GFX11-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v4, s2
; GFX11-NEXT:    v_mov_b32_e32 v3, s1
; GFX11-NEXT:    v_mov_b32_e32 v2, s0
; GFX11-NEXT:    ds_cmpstore_b64 v4, v[2:3], v[0:1] offset:32
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    buffer_gl0_inv
; GFX11-NEXT:    s_endpgm
  %gep = getelementptr i64, ptr addrspace(3) %ptr, i32 4
  %pair = cmpxchg ptr addrspace(3) %gep, i64 7, i64 %swap seq_cst monotonic
  %result = extractvalue { i64, i1 } %pair, 0
  ret void
}