blob: e6c68112d067fbd1f1fa1e6f91e42802b34cdb39 [file]
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx1250 -run-pass=instruction-select %s -o - | FileCheck -check-prefix=GCN %s
---
name: umin_s64_sv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umin_s64_sv
; GCN: liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...
---
name: umin_s64_vs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-LABEL: name: umin_s64_vs
; GCN: liveins: $vgpr0_vgpr1, $sgpr2_sgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:sgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $sgpr2_sgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...
---
name: umin_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: umin_s64_vv
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY $vgpr2_vgpr3
; GCN-NEXT: [[V_MIN_U64_e64_:%[0-9]+]]:vreg_64_align2 = V_MIN_U64_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MIN_U64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vgpr(s64) = G_UMIN %0, %1
S_ENDPGM 0, implicit %2
...