[SLP][NFC]Add a test with incorrect cost model for short-circuit or/and, modeled via select

llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll

diff --git a/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll b/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
new file mode 100644
index 0000000..3b2b6f6
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/select-logical-or-and-i1-vector.ll
@@ -0,0 +1,157 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-pc-linux-gnu -mattr=+avx512vl < %s | FileCheck %s
+
+; Verify that "select i1 %x, i1 true, i1 %y" (logical OR) and
+; "select i1 %x, i1 %y, i1 false" (logical AND) patterns are properly
+; costed as vector or/and, enabling SLP vectorization.
+; Reduced from a real-world molecular docking kernel where independent
+; scalar fcmps are combined with a loop-invariant scalar condition via
+; logical select, feeding into float selects stored to consecutive memory.
+
+define void @select_logical_or_i1(ptr %dst,
+; CHECK-LABEL: define void @select_logical_or_i1(
+; CHECK-SAME: ptr [[DST:%.*]], float [[D0:%.*]], float [[D1:%.*]], float [[D2:%.*]], float [[D3:%.*]], float [[THRESHOLD:%.*]], float [[HPHB_VAL:%.*]], i1 [[SCALAR_COND:%.*]], float [[Y0:%.*]], float [[Y1:%.*]], float [[Y2:%.*]], float [[Y3:%.*]], float [[E0:%.*]], float [[E1:%.*]], float [[E2:%.*]], float [[E3:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[CMP0:%.*]] = fcmp fast uge float [[D0]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp fast uge float [[D1]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp fast uge float [[D2]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP3:%.*]] = fcmp fast uge float [[D3]], [[THRESHOLD]]
+; CHECK-NEXT:    [[OR3:%.*]] = select i1 [[CMP3]], i1 true, i1 [[SCALAR_COND]]
+; CHECK-NEXT:    [[OR2:%.*]] = select i1 [[CMP2]], i1 true, i1 [[SCALAR_COND]]
+; CHECK-NEXT:    [[OR1:%.*]] = select i1 [[CMP1]], i1 true, i1 [[SCALAR_COND]]
+; CHECK-NEXT:    [[OR0:%.*]] = select i1 [[CMP0]], i1 true, i1 [[SCALAR_COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i1> poison, i1 [[OR0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i1> [[TMP0]], i1 [[OR1]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i1> [[TMP1]], i1 [[OR2]], i32 2
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x i1> [[TMP2]], i1 [[OR3]], i32 3
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i32 0
+; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP12:%.*]] = select <4 x i1> [[TMP9]], <4 x float> zeroinitializer, <4 x float> [[TMP11]]
+; CHECK-NEXT:    [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i32 0
+; CHECK-NEXT:    [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i32 1
+; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i32 2
+; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i32 3
+; CHECK-NEXT:    [[TMP17:%.*]] = fmul fast <4 x float> [[TMP12]], [[TMP16]]
+; CHECK-NEXT:    [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i32 1
+; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i32 2
+; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i32 3
+; CHECK-NEXT:    [[TMP22:%.*]] = fadd fast <4 x float> [[TMP21]], [[TMP17]]
+; CHECK-NEXT:    store <4 x float> [[TMP22]], ptr [[DST]], align 4
+; CHECK-NEXT:    ret void
+;
+  float %d0, float %d1, float %d2, float %d3,
+  float %threshold, float %hphb_val,
+  i1 %scalar_cond,
+  float %y0, float %y1, float %y2, float %y3,
+  float %e0, float %e1, float %e2, float %e3) {
+entry:
+  %cmp0 = fcmp fast uge float %d0, %threshold
+  %cmp1 = fcmp fast uge float %d1, %threshold
+  %cmp2 = fcmp fast uge float %d2, %threshold
+  %cmp3 = fcmp fast uge float %d3, %threshold
+
+  ; select i1 %cmp, i1 true, i1 %scalar_cond -> or i1 %cmp, %scalar_cond
+  %or0 = select i1 %cmp0, i1 true, i1 %scalar_cond
+  %or1 = select i1 %cmp1, i1 true, i1 %scalar_cond
+  %or2 = select i1 %cmp2, i1 true, i1 %scalar_cond
+  %or3 = select i1 %cmp3, i1 true, i1 %scalar_cond
+
+  %sel0 = select i1 %or0, float 0.000000e+00, float %hphb_val
+  %sel1 = select i1 %or1, float 0.000000e+00, float %hphb_val
+  %sel2 = select i1 %or2, float 0.000000e+00, float %hphb_val
+  %sel3 = select i1 %or3, float 0.000000e+00, float %hphb_val
+
+  %mul0 = fmul fast float %sel0, %y0
+  %mul1 = fmul fast float %sel1, %y1
+  %mul2 = fmul fast float %sel2, %y2
+  %mul3 = fmul fast float %sel3, %y3
+
+  %res0 = fadd fast float %e0, %mul0
+  %res1 = fadd fast float %e1, %mul1
+  %res2 = fadd fast float %e2, %mul2
+  %res3 = fadd fast float %e3, %mul3
+
+  store float %res0, ptr %dst, align 4
+  %p1 = getelementptr inbounds float, ptr %dst, i64 1
+  store float %res1, ptr %p1, align 4
+  %p2 = getelementptr inbounds float, ptr %dst, i64 2
+  store float %res2, ptr %p2, align 4
+  %p3 = getelementptr inbounds float, ptr %dst, i64 3
+  store float %res3, ptr %p3, align 4
+  ret void
+}
+
+define void @select_logical_and_i1(ptr %dst,
+; CHECK-LABEL: define void @select_logical_and_i1(
+; CHECK-SAME: ptr [[DST:%.*]], float [[D0:%.*]], float [[D1:%.*]], float [[D2:%.*]], float [[D3:%.*]], float [[THRESHOLD:%.*]], float [[HPHB_VAL:%.*]], i1 [[SCALAR_COND:%.*]], float [[Y0:%.*]], float [[Y1:%.*]], float [[Y2:%.*]], float [[Y3:%.*]], float [[E0:%.*]], float [[E1:%.*]], float [[E2:%.*]], float [[E3:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[CMP0:%.*]] = fcmp fast uge float [[D0]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp fast uge float [[D1]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp fast uge float [[D2]], [[THRESHOLD]]
+; CHECK-NEXT:    [[CMP3:%.*]] = fcmp fast uge float [[D3]], [[THRESHOLD]]
+; CHECK-NEXT:    [[AND3:%.*]] = select i1 [[CMP3]], i1 [[SCALAR_COND]], i1 false
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[CMP2]], i1 [[SCALAR_COND]], i1 false
+; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[CMP1]], i1 [[SCALAR_COND]], i1 false
+; CHECK-NEXT:    [[AND0:%.*]] = select i1 [[CMP0]], i1 [[SCALAR_COND]], i1 false
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i1> poison, i1 [[AND0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i1> [[TMP0]], i1 [[AND1]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i1> [[TMP1]], i1 [[AND2]], i32 2
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x i1> [[TMP2]], i1 [[AND3]], i32 3
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x float> poison, float [[HPHB_VAL]], i32 0
+; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <4 x float> [[TMP10]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP12:%.*]] = select <4 x i1> [[TMP9]], <4 x float> zeroinitializer, <4 x float> [[TMP11]]
+; CHECK-NEXT:    [[TMP13:%.*]] = insertelement <4 x float> poison, float [[Y0]], i32 0
+; CHECK-NEXT:    [[TMP14:%.*]] = insertelement <4 x float> [[TMP13]], float [[Y1]], i32 1
+; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <4 x float> [[TMP14]], float [[Y2]], i32 2
+; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <4 x float> [[TMP15]], float [[Y3]], i32 3
+; CHECK-NEXT:    [[TMP17:%.*]] = fmul fast <4 x float> [[TMP12]], [[TMP16]]
+; CHECK-NEXT:    [[TMP18:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <4 x float> [[TMP18]], float [[E1]], i32 1
+; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x float> [[TMP19]], float [[E2]], i32 2
+; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x float> [[TMP20]], float [[E3]], i32 3
+; CHECK-NEXT:    [[TMP22:%.*]] = fadd fast <4 x float> [[TMP21]], [[TMP17]]
+; CHECK-NEXT:    store <4 x float> [[TMP22]], ptr [[DST]], align 4
+; CHECK-NEXT:    ret void
+;
+  float %d0, float %d1, float %d2, float %d3,
+  float %threshold, float %hphb_val,
+  i1 %scalar_cond,
+  float %y0, float %y1, float %y2, float %y3,
+  float %e0, float %e1, float %e2, float %e3) {
+entry:
+  %cmp0 = fcmp fast uge float %d0, %threshold
+  %cmp1 = fcmp fast uge float %d1, %threshold
+  %cmp2 = fcmp fast uge float %d2, %threshold
+  %cmp3 = fcmp fast uge float %d3, %threshold
+
+  ; select i1 %cmp, i1 %scalar_cond, i1 false -> and i1 %cmp, %scalar_cond
+  %and0 = select i1 %cmp0, i1 %scalar_cond, i1 false
+  %and1 = select i1 %cmp1, i1 %scalar_cond, i1 false
+  %and2 = select i1 %cmp2, i1 %scalar_cond, i1 false
+  %and3 = select i1 %cmp3, i1 %scalar_cond, i1 false
+
+  %sel0 = select i1 %and0, float 0.000000e+00, float %hphb_val
+  %sel1 = select i1 %and1, float 0.000000e+00, float %hphb_val
+  %sel2 = select i1 %and2, float 0.000000e+00, float %hphb_val
+  %sel3 = select i1 %and3, float 0.000000e+00, float %hphb_val
+
+  %mul0 = fmul fast float %sel0, %y0
+  %mul1 = fmul fast float %sel1, %y1
+  %mul2 = fmul fast float %sel2, %y2
+  %mul3 = fmul fast float %sel3, %y3
+
+  %res0 = fadd fast float %e0, %mul0
+  %res1 = fadd fast float %e1, %mul1
+  %res2 = fadd fast float %e2, %mul2
+  %res3 = fadd fast float %e3, %mul3
+
+  store float %res0, ptr %dst, align 4
+  %p1 = getelementptr inbounds float, ptr %dst, i64 1
+  store float %res1, ptr %p1, align 4
+  %p2 = getelementptr inbounds float, ptr %dst, i64 2
+  store float %res2, ptr %p2, align 4
+  %p3 = getelementptr inbounds float, ptr %dst, i64 3
+  store float %res3, ptr %p3, align 4
+  ret void
+}