llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s

define void @h(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o) {
; CHECK-LABEL: define void @h(
; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i16 [[C:%.*]], i16 [[D:%.*]], i16 [[E:%.*]], i16 [[F:%.*]], i16 [[G:%.*]], i16 [[H:%.*]], i16 [[I:%.*]], i16 [[J:%.*]], i16 [[K:%.*]], i16 [[L:%.*]], i16 [[M:%.*]], i16 [[N:%.*]], i16 [[O:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[CONV9:%.*]] = zext i16 [[A]] to i32
; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
; CHECK-NEXT:    [[CONV310:%.*]] = zext i16 [[B]] to i32
; CHECK-NEXT:    [[ADD4:%.*]] = or i32 [[CONV310]], [[CONV9]]
; CHECK-NEXT:    [[SUB:%.*]] = or i32 [[CONV9]], [[CONV310]]
; CHECK-NEXT:    [[CONV15:%.*]] = sext i16 [[C]] to i32
; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr i8, ptr null, i64 24
; CHECK-NEXT:    [[CONV19:%.*]] = sext i16 [[D]] to i32
; CHECK-NEXT:    [[SUB20:%.*]] = or i32 [[SHR]], [[CONV19]]
; CHECK-NEXT:    [[SHR29:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ADD30:%.*]] = or i32 [[SHR29]], [[CONV15]]
; CHECK-NEXT:    [[SUB39:%.*]] = or i32 [[SUB]], [[SUB20]]
; CHECK-NEXT:    [[CONV40:%.*]] = trunc i32 [[SUB39]] to i16
; CHECK-NEXT:    store i16 [[CONV40]], ptr [[ARRAYIDX2]], align 2
; CHECK-NEXT:    [[SUB44:%.*]] = or i32 [[ADD4]], [[ADD30]]
; CHECK-NEXT:    [[CONV45:%.*]] = trunc i32 [[SUB44]] to i16
; CHECK-NEXT:    store i16 [[CONV45]], ptr [[ARRAYIDX18]], align 2
; CHECK-NEXT:    [[ARRAYIDX2_1:%.*]] = getelementptr i8, ptr null, i64 18
; CHECK-NEXT:    [[CONV3_112:%.*]] = zext i16 [[E]] to i32
; CHECK-NEXT:    [[ADD4_1:%.*]] = or i32 [[CONV3_112]], 0
; CHECK-NEXT:    [[SUB_1:%.*]] = or i32 0, [[CONV3_112]]
; CHECK-NEXT:    [[CONV15_1:%.*]] = sext i16 [[F]] to i32
; CHECK-NEXT:    [[SHR_1:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ARRAYIDX18_1:%.*]] = getelementptr i8, ptr null, i64 26
; CHECK-NEXT:    [[CONV19_1:%.*]] = sext i16 [[G]] to i32
; CHECK-NEXT:    [[SUB20_1:%.*]] = or i32 [[SHR_1]], [[CONV19_1]]
; CHECK-NEXT:    [[SHR29_1:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ADD30_1:%.*]] = or i32 [[SHR29_1]], [[CONV15_1]]
; CHECK-NEXT:    [[SUB39_1:%.*]] = or i32 [[SUB_1]], [[SUB20_1]]
; CHECK-NEXT:    [[CONV40_1:%.*]] = trunc i32 [[SUB39_1]] to i16
; CHECK-NEXT:    store i16 [[CONV40_1]], ptr [[ARRAYIDX2_1]], align 2
; CHECK-NEXT:    [[SUB44_1:%.*]] = or i32 [[ADD4_1]], [[ADD30_1]]
; CHECK-NEXT:    [[CONV45_1:%.*]] = trunc i32 [[SUB44_1]] to i16
; CHECK-NEXT:    store i16 [[CONV45_1]], ptr [[ARRAYIDX18_1]], align 2
; CHECK-NEXT:    [[CONV_213:%.*]] = zext i16 [[H]] to i32
; CHECK-NEXT:    [[ARRAYIDX2_2:%.*]] = getelementptr i8, ptr null, i64 20
; CHECK-NEXT:    [[CONV3_214:%.*]] = zext i16 [[I]] to i32
; CHECK-NEXT:    [[ADD4_2:%.*]] = or i32 0, [[CONV_213]]
; CHECK-NEXT:    [[SUB_2:%.*]] = or i32 0, [[CONV3_214]]
; CHECK-NEXT:    [[CONV15_2:%.*]] = sext i16 [[J]] to i32
; CHECK-NEXT:    [[SHR_2:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ARRAYIDX18_2:%.*]] = getelementptr i8, ptr null, i64 28
; CHECK-NEXT:    [[CONV19_2:%.*]] = sext i16 [[K]] to i32
; CHECK-NEXT:    [[SUB20_2:%.*]] = or i32 [[SHR_2]], [[CONV19_2]]
; CHECK-NEXT:    [[SHR29_2:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ADD30_2:%.*]] = or i32 [[SHR29_2]], [[CONV15_2]]
; CHECK-NEXT:    [[SUB39_2:%.*]] = or i32 [[SUB_2]], [[SUB20_2]]
; CHECK-NEXT:    [[CONV40_2:%.*]] = trunc i32 [[SUB39_2]] to i16
; CHECK-NEXT:    store i16 [[CONV40_2]], ptr [[ARRAYIDX2_2]], align 2
; CHECK-NEXT:    [[SUB44_2:%.*]] = or i32 [[ADD4_2]], [[ADD30_2]]
; CHECK-NEXT:    [[CONV45_2:%.*]] = trunc i32 [[SUB44_2]] to i16
; CHECK-NEXT:    store i16 [[CONV45_2]], ptr [[ARRAYIDX18_2]], align 2
; CHECK-NEXT:    [[CONV_315:%.*]] = zext i16 [[L]] to i32
; CHECK-NEXT:    [[ARRAYIDX2_3:%.*]] = getelementptr i8, ptr null, i64 22
; CHECK-NEXT:    [[CONV3_316:%.*]] = zext i16 [[M]] to i32
; CHECK-NEXT:    [[ADD4_3:%.*]] = or i32 0, [[CONV_315]]
; CHECK-NEXT:    [[SUB_3:%.*]] = or i32 0, [[CONV3_316]]
; CHECK-NEXT:    [[CONV15_3:%.*]] = sext i16 [[N]] to i32
; CHECK-NEXT:    [[SHR_3:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ARRAYIDX18_3:%.*]] = getelementptr i8, ptr null, i64 30
; CHECK-NEXT:    [[CONV19_3:%.*]] = sext i16 [[O]] to i32
; CHECK-NEXT:    [[SUB20_3:%.*]] = or i32 [[SHR_3]], [[CONV19_3]]
; CHECK-NEXT:    [[SHR29_3:%.*]] = ashr i32 0, 0
; CHECK-NEXT:    [[ADD30_3:%.*]] = or i32 [[SHR29_3]], [[CONV15_3]]
; CHECK-NEXT:    [[SUB39_3:%.*]] = or i32 [[SUB_3]], [[SUB20_3]]
; CHECK-NEXT:    [[CONV40_3:%.*]] = trunc i32 [[SUB39_3]] to i16
; CHECK-NEXT:    store i16 [[CONV40_3]], ptr [[ARRAYIDX2_3]], align 2
; CHECK-NEXT:    [[SUB44_3:%.*]] = or i32 [[ADD4_3]], [[ADD30_3]]
; CHECK-NEXT:    [[CONV45_3:%.*]] = trunc i32 [[SUB44_3]] to i16
; CHECK-NEXT:    store i16 [[CONV45_3]], ptr [[ARRAYIDX18_3]], align 2
; CHECK-NEXT:    ret void
;
entry:
  %conv9 = zext i16 %a to i32
  %arrayidx2 = getelementptr i8, ptr null, i64 16
  %conv310 = zext i16 %b to i32
  %add4 = or i32 %conv310, %conv9
  %sub = or i32 %conv9, %conv310
  %conv15 = sext i16 %c to i32
  %shr = ashr i32 0, 0
  %arrayidx18 = getelementptr i8, ptr null, i64 24
  %conv19 = sext i16 %d to i32
  %sub20 = or i32 %shr, %conv19
  %shr29 = ashr i32 0, 0
  %add30 = or i32 %shr29, %conv15
  %sub39 = or i32 %sub, %sub20
  %conv40 = trunc i32 %sub39 to i16
  store i16 %conv40, ptr %arrayidx2, align 2
  %sub44 = or i32 %add4, %add30
  %conv45 = trunc i32 %sub44 to i16
  store i16 %conv45, ptr %arrayidx18, align 2
  %arrayidx2.1 = getelementptr i8, ptr null, i64 18
  %conv3.112 = zext i16 %e to i32
  %add4.1 = or i32 %conv3.112, 0
  %sub.1 = or i32 0, %conv3.112
  %conv15.1 = sext i16 %f to i32
  %shr.1 = ashr i32 0, 0
  %arrayidx18.1 = getelementptr i8, ptr null, i64 26
  %conv19.1 = sext i16 %g to i32
  %sub20.1 = or i32 %shr.1, %conv19.1
  %shr29.1 = ashr i32 0, 0
  %add30.1 = or i32 %shr29.1, %conv15.1
  %sub39.1 = or i32 %sub.1, %sub20.1
  %conv40.1 = trunc i32 %sub39.1 to i16
  store i16 %conv40.1, ptr %arrayidx2.1, align 2
  %sub44.1 = or i32 %add4.1, %add30.1
  %conv45.1 = trunc i32 %sub44.1 to i16
  store i16 %conv45.1, ptr %arrayidx18.1, align 2
  %conv.213 = zext i16 %h to i32
  %arrayidx2.2 = getelementptr i8, ptr null, i64 20
  %conv3.214 = zext i16 %i to i32
  %add4.2 = or i32 0, %conv.213
  %sub.2 = or i32 0, %conv3.214
  %conv15.2 = sext i16 %j to i32
  %shr.2 = ashr i32 0, 0
  %arrayidx18.2 = getelementptr i8, ptr null, i64 28
  %conv19.2 = sext i16 %k to i32
  %sub20.2 = or i32 %shr.2, %conv19.2
  %shr29.2 = ashr i32 0, 0
  %add30.2 = or i32 %shr29.2, %conv15.2
  %sub39.2 = or i32 %sub.2, %sub20.2
  %conv40.2 = trunc i32 %sub39.2 to i16
  store i16 %conv40.2, ptr %arrayidx2.2, align 2
  %sub44.2 = or i32 %add4.2, %add30.2
  %conv45.2 = trunc i32 %sub44.2 to i16
  store i16 %conv45.2, ptr %arrayidx18.2, align 2
  %conv.315 = zext i16 %l to i32
  %arrayidx2.3 = getelementptr i8, ptr null, i64 22
  %conv3.316 = zext i16 %m to i32
  %add4.3 = or i32 0, %conv.315
  %sub.3 = or i32 0, %conv3.316
  %conv15.3 = sext i16 %n to i32
  %shr.3 = ashr i32 0, 0
  %arrayidx18.3 = getelementptr i8, ptr null, i64 30
  %conv19.3 = sext i16 %o to i32
  %sub20.3 = or i32 %shr.3, %conv19.3
  %shr29.3 = ashr i32 0, 0
  %add30.3 = or i32 %shr29.3, %conv15.3
  %sub39.3 = or i32 %sub.3, %sub20.3
  %conv40.3 = trunc i32 %sub39.3 to i16
  store i16 %conv40.3, ptr %arrayidx2.3, align 2
  %sub44.3 = or i32 %add4.3, %add30.3
  %conv45.3 = trunc i32 %sub44.3 to i16
  store i16 %conv45.3, ptr %arrayidx18.3, align 2
  ret void
}