llvm/test/CodeGen/RISCV/rvv/pr141907.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv64 -mcpu=sifive-p670 | FileCheck %s

define void @pr141907(ptr %0) nounwind {
; CHECK-LABEL: pr141907:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    csrr a1, vlenb
; CHECK-NEXT:    slli a1, a1, 2
; CHECK-NEXT:    sub sp, sp, a1
; CHECK-NEXT:    vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmclr.m v0
; CHECK-NEXT:    li a1, 0
; CHECK-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v10, 0
; CHECK-NEXT:    addi a2, sp, 16
; CHECK-NEXT:    addi a3, sp, 20
; CHECK-NEXT:    li a4, 12
; CHECK-NEXT:  .LBB0_1: # %vector.body
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    vs4r.v v8, (a2)
; CHECK-NEXT:    vsetvli a1, a1, e8, mf8, ta, ma
; CHECK-NEXT:    vsetivli zero, 0, e16, mf2, ta, ma
; CHECK-NEXT:    vnsrl.wi v9, v8, 0, v0.t
; CHECK-NEXT:    vsetvli a5, zero, e32, m1, ta, ma
; CHECK-NEXT:    vlse32.v v8, (a3), a4
; CHECK-NEXT:    vsetivli zero, 0, e16, mf2, ta, ma
; CHECK-NEXT:    vsseg2e16.v v9, (zero)
; CHECK-NEXT:    bnez a1, .LBB0_1
; CHECK-NEXT:  .LBB0_2: # %while.body5
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT:    vse16.v v8, (a0)
; CHECK-NEXT:    j .LBB0_2
entry:
  br label %vector.body

vector.body:                                      ; preds = %vector.body, %entry
  %evl.based.iv = phi i64 [ 0, %entry ], [ %2, %vector.body ]
  %vector.recur = phi <vscale x 2 x i32> [ zeroinitializer, %entry ], [ %3, %vector.body ]
  %1 = call i32 @llvm.experimental.get.vector.length.i64(i64 %evl.based.iv, i32 1, i1 true)
  %2 = zext i32 %1 to i64
  %wide.masked.load = call <vscale x 6 x i32> @llvm.vp.load.nxv6i32.p0(ptr null, <vscale x 6 x i1> zeroinitializer, i32 0)
  %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3.nxv6i32(<vscale x 6 x i32> %wide.masked.load)
  %3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1
  %vp.cast65 = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %vector.recur, <vscale x 2 x i1> zeroinitializer, i32 0)
  %interleaved.vec = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %vp.cast65, <vscale x 2 x i16> zeroinitializer)
  call void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16> %interleaved.vec, ptr null, <vscale x 4 x i1> splat (i1 true), i32 0)
  %4 = icmp eq i32 %1, 0
  br i1 %4, label %while.body5, label %vector.body

while.body5:                                      ; preds = %while.body5, %vector.body
  %5 = bitcast <vscale x 2 x i32> %3 to <vscale x 4 x i16>
  %cond52 = extractelement <vscale x 4 x i16> %5, i64 0
  store i16 %cond52, ptr %0, align 2
  br label %while.body5
}