llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32I-DEFAULT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I-DEFAULT %s
; RUN: llc -mtriple=riscv32 -M emit-x8-as-fp -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32I-EMIT-FP %s
; RUN: llc -mtriple=riscv64 -M emit-x8-as-fp -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I-EMIT-FP %s
; RUN: llc -mtriple=riscv32 -M numeric -M emit-x8-as-fp -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV32I-NUMERIC %s
; RUN: llc -mtriple=riscv64 -M numeric -M emit-x8-as-fp -verify-machineinstrs \
; RUN:   < %s | FileCheck -check-prefix=RV64I-NUMERIC %s

define signext i32 @add(i32 %0, i32 %1) #0 {
; RV32I-DEFAULT-LABEL: add:
; RV32I-DEFAULT:       # %bb.0:
; RV32I-DEFAULT-NEXT:    addi sp, sp, -16
; RV32I-DEFAULT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-DEFAULT-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-DEFAULT-NEXT:    addi s0, sp, 16
; RV32I-DEFAULT-NEXT:    sw a0, -12(s0)
; RV32I-DEFAULT-NEXT:    sw a1, -16(s0)
; RV32I-DEFAULT-NEXT:    lw a0, -12(s0)
; RV32I-DEFAULT-NEXT:    lw a1, -16(s0)
; RV32I-DEFAULT-NEXT:    add a0, a0, a1
; RV32I-DEFAULT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-DEFAULT-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-DEFAULT-NEXT:    addi sp, sp, 16
; RV32I-DEFAULT-NEXT:    ret
;
; RV64I-DEFAULT-LABEL: add:
; RV64I-DEFAULT:       # %bb.0:
; RV64I-DEFAULT-NEXT:    addi sp, sp, -32
; RV64I-DEFAULT-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-DEFAULT-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-DEFAULT-NEXT:    addi s0, sp, 32
; RV64I-DEFAULT-NEXT:    sw a0, -20(s0)
; RV64I-DEFAULT-NEXT:    sw a1, -24(s0)
; RV64I-DEFAULT-NEXT:    lw a0, -20(s0)
; RV64I-DEFAULT-NEXT:    lw a1, -24(s0)
; RV64I-DEFAULT-NEXT:    addw a0, a0, a1
; RV64I-DEFAULT-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-DEFAULT-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-DEFAULT-NEXT:    addi sp, sp, 32
; RV64I-DEFAULT-NEXT:    ret
;
; RV32I-EMIT-FP-LABEL: add:
; RV32I-EMIT-FP:       # %bb.0:
; RV32I-EMIT-FP-NEXT:    addi sp, sp, -16
; RV32I-EMIT-FP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-EMIT-FP-NEXT:    sw fp, 8(sp) # 4-byte Folded Spill
; RV32I-EMIT-FP-NEXT:    addi fp, sp, 16
; RV32I-EMIT-FP-NEXT:    sw a0, -12(fp)
; RV32I-EMIT-FP-NEXT:    sw a1, -16(fp)
; RV32I-EMIT-FP-NEXT:    lw a0, -12(fp)
; RV32I-EMIT-FP-NEXT:    lw a1, -16(fp)
; RV32I-EMIT-FP-NEXT:    add a0, a0, a1
; RV32I-EMIT-FP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-EMIT-FP-NEXT:    lw fp, 8(sp) # 4-byte Folded Reload
; RV32I-EMIT-FP-NEXT:    addi sp, sp, 16
; RV32I-EMIT-FP-NEXT:    ret
;
; RV64I-EMIT-FP-LABEL: add:
; RV64I-EMIT-FP:       # %bb.0:
; RV64I-EMIT-FP-NEXT:    addi sp, sp, -32
; RV64I-EMIT-FP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-EMIT-FP-NEXT:    sd fp, 16(sp) # 8-byte Folded Spill
; RV64I-EMIT-FP-NEXT:    addi fp, sp, 32
; RV64I-EMIT-FP-NEXT:    sw a0, -20(fp)
; RV64I-EMIT-FP-NEXT:    sw a1, -24(fp)
; RV64I-EMIT-FP-NEXT:    lw a0, -20(fp)
; RV64I-EMIT-FP-NEXT:    lw a1, -24(fp)
; RV64I-EMIT-FP-NEXT:    addw a0, a0, a1
; RV64I-EMIT-FP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-EMIT-FP-NEXT:    ld fp, 16(sp) # 8-byte Folded Reload
; RV64I-EMIT-FP-NEXT:    addi sp, sp, 32
; RV64I-EMIT-FP-NEXT:    ret
;
; RV32I-NUMERIC-LABEL: add:
; RV32I-NUMERIC:       # %bb.0:
; RV32I-NUMERIC-NEXT:    addi x2, x2, -16
; RV32I-NUMERIC-NEXT:    sw x1, 12(x2) # 4-byte Folded Spill
; RV32I-NUMERIC-NEXT:    sw x8, 8(x2) # 4-byte Folded Spill
; RV32I-NUMERIC-NEXT:    addi x8, x2, 16
; RV32I-NUMERIC-NEXT:    sw x10, -12(x8)
; RV32I-NUMERIC-NEXT:    sw x11, -16(x8)
; RV32I-NUMERIC-NEXT:    lw x10, -12(x8)
; RV32I-NUMERIC-NEXT:    lw x11, -16(x8)
; RV32I-NUMERIC-NEXT:    add x10, x10, x11
; RV32I-NUMERIC-NEXT:    lw x1, 12(x2) # 4-byte Folded Reload
; RV32I-NUMERIC-NEXT:    lw x8, 8(x2) # 4-byte Folded Reload
; RV32I-NUMERIC-NEXT:    addi x2, x2, 16
; RV32I-NUMERIC-NEXT:    ret
;
; RV64I-NUMERIC-LABEL: add:
; RV64I-NUMERIC:       # %bb.0:
; RV64I-NUMERIC-NEXT:    addi x2, x2, -32
; RV64I-NUMERIC-NEXT:    sd x1, 24(x2) # 8-byte Folded Spill
; RV64I-NUMERIC-NEXT:    sd x8, 16(x2) # 8-byte Folded Spill
; RV64I-NUMERIC-NEXT:    addi x8, x2, 32
; RV64I-NUMERIC-NEXT:    sw x10, -20(x8)
; RV64I-NUMERIC-NEXT:    sw x11, -24(x8)
; RV64I-NUMERIC-NEXT:    lw x10, -20(x8)
; RV64I-NUMERIC-NEXT:    lw x11, -24(x8)
; RV64I-NUMERIC-NEXT:    addw x10, x10, x11
; RV64I-NUMERIC-NEXT:    ld x1, 24(x2) # 8-byte Folded Reload
; RV64I-NUMERIC-NEXT:    ld x8, 16(x2) # 8-byte Folded Reload
; RV64I-NUMERIC-NEXT:    addi x2, x2, 32
; RV64I-NUMERIC-NEXT:    ret
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  store i32 %0, ptr %3, align 4
  store i32 %1, ptr %4, align 4
  %5 = load i32, ptr %3, align 4
  %6 = load i32, ptr %4, align 4
  %7 = add nsw i32 %5, %6
  ret i32 %7
}

attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }