llvm/test/Transforms/SLPVectorizer/RISCV/split-vectorize-parent-for-copyables.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv32-unknown-linux-gnu -mattr=+v < %s | FileCheck %s

define i1 @test(i32 %0, i32 %add21.i, i32 %1) #0 {
; CHECK-LABEL: define i1 @test(
; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[ADD21_I:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0
; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP4:%.*]] = sub <4 x i32> zeroinitializer, [[TMP6]]
; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP0]], 1
; CHECK-NEXT:    [[DIFF_CHECK134:%.*]] = icmp eq i32 [[TMP3]], 0
; CHECK-NEXT:    [[DIFF_CHECK138:%.*]] = icmp ult i32 [[TMP3]], [[TMP1]]
; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP0]], [[TMP0]]
; CHECK-NEXT:    [[DIFF_CHECK142:%.*]] = icmp eq i32 [[TMP5]], 0
; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[ADD21_I]], i32 0
; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 4, i32 1, i32 2, i32 3>
; CHECK-NEXT:    [[TMP9:%.*]] = icmp ugt <4 x i32> [[TMP8]], [[TMP4]]
; CHECK-NEXT:    [[DIFF_CHECK149:%.*]] = icmp ult i32 [[TMP3]], [[ADD21_I]]
; CHECK-NEXT:    [[TMP10:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP9]])
; CHECK-NEXT:    [[CONFLICT_RDX147:%.*]] = or i1 [[TMP10]], [[DIFF_CHECK138]]
; CHECK-NEXT:    [[DIFF_CHECK148:%.*]] = or i1 [[DIFF_CHECK149]], [[DIFF_CHECK134]]
; CHECK-NEXT:    [[CONFLICT_RDX149:%.*]] = or i1 [[CONFLICT_RDX147]], [[DIFF_CHECK148]]
; CHECK-NEXT:    [[OP_RDX3:%.*]] = or i1 [[CONFLICT_RDX149]], [[DIFF_CHECK142]]
; CHECK-NEXT:    ret i1 [[OP_RDX3]]
;
entry:
  %2 = sub i32 0, %0
  %diff.check132 = icmp ugt i32 %add21.i, %2
  %3 = shl i32 %0, 1
  %diff.check134 = icmp eq i32 %3, 0
  %conflict.rdx135 = or i1 %diff.check132, %diff.check134
  %4 = sub i32 0, %0
  %diff.check136 = icmp ugt i32 %0, %4
  %conflict.rdx137 = or i1 %conflict.rdx135, %diff.check136
  %diff.check138 = icmp ult i32 %3, %1
  %conflict.rdx139 = or i1 %conflict.rdx137, %diff.check138
  %diff.check140 = icmp ugt i32 %0, %2
  %conflict.rdx141 = or i1 %conflict.rdx139, %diff.check140
  %5 = mul i32 %0, %0
  %diff.check142 = icmp eq i32 %5, 0
  %conflict.rdx143 = or i1 %conflict.rdx141, %diff.check142
  %6 = sub i32 0, %0
  %diff.check146 = icmp ugt i32 %0, %6
  %conflict.rdx147 = or i1 %conflict.rdx143, %diff.check146
  %diff.check148 = icmp ult i32 %3, %add21.i
  %conflict.rdx149 = or i1 %conflict.rdx147, %diff.check148
  ret i1 %conflict.rdx149
}