llvm/test/CodeGen/X86/srem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefixes=SSE,SSE4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2    | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512

define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
; SSE2-LABEL: fold_srem_vec_1:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movq {{.*#+}} xmm2 = [1,0,0,65535,0,0,0,0]
; SSE2-NEXT:    pmullw %xmm0, %xmm2
; SSE2-NEXT:    movq {{.*#+}} xmm1 = [44151,48623,2675,32081,0,0,0,0]
; SSE2-NEXT:    pmulhw %xmm0, %xmm1
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm3
; SSE2-NEXT:    pand %xmm2, %xmm3
; SSE2-NEXT:    movdqa %xmm1, %xmm4
; SSE2-NEXT:    psraw $8, %xmm4
; SSE2-NEXT:    pandn %xmm4, %xmm2
; SSE2-NEXT:    por %xmm3, %xmm2
; SSE2-NEXT:    movdqa %xmm1, %xmm3
; SSE2-NEXT:    psraw $4, %xmm3
; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3]
; SSE2-NEXT:    movaps %xmm2, %xmm3
; SSE2-NEXT:    psraw $1, %xmm3
; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [65535,0,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    psraw $2, %xmm2
; SSE2-NEXT:    movdqa {{.*#+}} xmm5 = [0,65535,0,65535,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm6
; SSE2-NEXT:    pand %xmm5, %xmm6
; SSE2-NEXT:    pandn %xmm2, %xmm5
; SSE2-NEXT:    por %xmm6, %xmm5
; SSE2-NEXT:    pand %xmm4, %xmm5
; SSE2-NEXT:    pandn %xmm3, %xmm4
; SSE2-NEXT:    por %xmm5, %xmm4
; SSE2-NEXT:    psrlw $15, %xmm1
; SSE2-NEXT:    paddw %xmm4, %xmm1
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [95,65412,98,64533,u,u,u,u]
; SSE2-NEXT:    psubw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: fold_srem_vec_1:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [1,0,0,65535,0,0,0,0]
; SSE4-NEXT:    pmullw %xmm0, %xmm1
; SSE4-NEXT:    movq {{.*#+}} xmm2 = [44151,48623,2675,32081,0,0,0,0]
; SSE4-NEXT:    pmulhw %xmm0, %xmm2
; SSE4-NEXT:    paddw %xmm1, %xmm2
; SSE4-NEXT:    movdqa %xmm2, %xmm1
; SSE4-NEXT:    psrlw $15, %xmm1
; SSE4-NEXT:    pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [1024,2048,16384,128,u,u,u,u]
; SSE4-NEXT:    paddw %xmm1, %xmm2
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [95,65412,98,64533,u,u,u,u]
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: fold_srem_vec_1:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,0,0,65535,u,u,u,u]
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [44151,48623,2675,32081,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX1OR2-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1024,2048,16384,128,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: fold_srem_vec_1:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,0,0,65535,u,u,u,u]
; AVX512-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [44151,48623,2675,32081,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX512-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX512-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,65412,98,64533,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
  ret <4 x i16> %1
}

define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
; SSE-LABEL: fold_srem_vec_2:
; SSE:       # %bb.0:
; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE-NEXT:    pmulhw %xmm0, %xmm1
; SSE-NEXT:    paddw %xmm0, %xmm1
; SSE-NEXT:    movdqa %xmm1, %xmm2
; SSE-NEXT:    psrlw $15, %xmm2
; SSE-NEXT:    psraw $6, %xmm1
; SSE-NEXT:    paddw %xmm2, %xmm1
; SSE-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [95,95,95,95,u,u,u,u]
; SSE-NEXT:    psubw %xmm1, %xmm0
; SSE-NEXT:    retq
;
; AVX-LABEL: fold_srem_vec_2:
; AVX:       # %bb.0:
; AVX-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,u,u,u,u]
; AVX-NEXT:    vpaddw %xmm0, %xmm1, %xmm1
; AVX-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX-NEXT:    vpsraw $6, %xmm1, %xmm1
; AVX-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,95,95,95,u,u,u,u]
; AVX-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  ret <4 x i16> %1
}


; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
; SSE2-LABEL: combine_srem_sdiv:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE2-NEXT:    pmulhw %xmm0, %xmm1
; SSE2-NEXT:    paddw %xmm0, %xmm1
; SSE2-NEXT:    movdqa %xmm1, %xmm2
; SSE2-NEXT:    psrlw $15, %xmm2
; SSE2-NEXT:    psraw $6, %xmm1
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [95,95,95,95,u,u,u,u]
; SSE2-NEXT:    pmullw %xmm1, %xmm2
; SSE2-NEXT:    psubw %xmm2, %xmm0
; SSE2-NEXT:    paddw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: combine_srem_sdiv:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE4-NEXT:    pmulhw %xmm0, %xmm1
; SSE4-NEXT:    paddw %xmm0, %xmm1
; SSE4-NEXT:    movdqa %xmm1, %xmm2
; SSE4-NEXT:    psrlw $15, %xmm2
; SSE4-NEXT:    psraw $6, %xmm1
; SSE4-NEXT:    paddw %xmm2, %xmm1
; SSE4-NEXT:    pmovsxbw {{.*#+}} xmm2 = [95,95,95,95,95,95,95,95]
; SSE4-NEXT:    pmullw %xmm1, %xmm2
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    paddw %xmm1, %xmm0
; SSE4-NEXT:    retq
;
; AVX-LABEL: combine_srem_sdiv:
; AVX:       # %bb.0:
; AVX-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,u,u,u,u]
; AVX-NEXT:    vpaddw %xmm0, %xmm1, %xmm1
; AVX-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX-NEXT:    vpsraw $6, %xmm1, %xmm1
; AVX-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [95,95,95,95,u,u,u,u]
; AVX-NEXT:    vpsubw %xmm2, %xmm0, %xmm0
; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  %3 = add <4 x i16> %1, %2
  ret <4 x i16> %3
}

; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
; SSE2-LABEL: dont_fold_srem_power_of_two:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movq {{.*#+}} xmm1 = [32769,32769,32769,44151,0,0,0,0]
; SSE2-NEXT:    pmulhw %xmm0, %xmm1
; SSE2-NEXT:    paddw %xmm0, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [0,0,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm3
; SSE2-NEXT:    pand %xmm2, %xmm3
; SSE2-NEXT:    movdqa %xmm1, %xmm4
; SSE2-NEXT:    psraw $4, %xmm4
; SSE2-NEXT:    pandn %xmm4, %xmm2
; SSE2-NEXT:    por %xmm3, %xmm2
; SSE2-NEXT:    movdqa %xmm2, %xmm3
; SSE2-NEXT:    psraw $2, %xmm3
; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[0,0]
; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[2,0],xmm2[2,3]
; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT:    andps %xmm2, %xmm3
; SSE2-NEXT:    movdqa %xmm1, %xmm4
; SSE2-NEXT:    psraw $5, %xmm4
; SSE2-NEXT:    andnps %xmm4, %xmm2
; SSE2-NEXT:    orps %xmm3, %xmm2
; SSE2-NEXT:    psrlw $15, %xmm1
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [64,32,8,95,u,u,u,u]
; SSE2-NEXT:    psubw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_srem_power_of_two:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [32769,32769,32769,44151,0,0,0,0]
; SSE4-NEXT:    pmulhw %xmm0, %xmm1
; SSE4-NEXT:    paddw %xmm0, %xmm1
; SSE4-NEXT:    movdqa %xmm1, %xmm2
; SSE4-NEXT:    psrlw $15, %xmm2
; SSE4-NEXT:    pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [2048,4096,16384,1024,u,u,u,u]
; SSE4-NEXT:    paddw %xmm2, %xmm1
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [64,32,8,95,u,u,u,u]
; SSE4-NEXT:    psubw %xmm1, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: dont_fold_srem_power_of_two:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [32769,32769,32769,44151,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm0, %xmm1, %xmm1
; AVX1OR2-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [2048,4096,16384,1024,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_srem_power_of_two:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [32769,32769,32769,44151,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm0, %xmm1, %xmm1
; AVX512-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX512-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
  ret <4 x i16> %1
}

; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
; SSE2-LABEL: dont_fold_srem_one:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movq {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0]
; SSE2-NEXT:    pand %xmm0, %xmm1
; SSE2-NEXT:    movq {{.*#+}} xmm2 = [0,12827,45591,12375,0,0,0,0]
; SSE2-NEXT:    pmulhw %xmm0, %xmm2
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [65535,0,0,65535,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm4
; SSE2-NEXT:    pand %xmm3, %xmm4
; SSE2-NEXT:    movdqa %xmm1, %xmm5
; SSE2-NEXT:    psraw $4, %xmm5
; SSE2-NEXT:    pandn %xmm5, %xmm3
; SSE2-NEXT:    por %xmm4, %xmm3
; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [65535,0,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    pand %xmm4, %xmm3
; SSE2-NEXT:    movdqa %xmm2, %xmm5
; SSE2-NEXT:    psraw $10, %xmm5
; SSE2-NEXT:    pandn %xmm5, %xmm4
; SSE2-NEXT:    por %xmm3, %xmm4
; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [65535,0,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT:    pand %xmm3, %xmm4
; SSE2-NEXT:    psraw $7, %xmm2
; SSE2-NEXT:    pandn %xmm2, %xmm3
; SSE2-NEXT:    por %xmm4, %xmm3
; SSE2-NEXT:    psrlw $15, %xmm1
; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT:    paddw %xmm3, %xmm1
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1,654,23,5423,u,u,u,u]
; SSE2-NEXT:    psubw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_srem_one:
; SSE4:       # %bb.0:
; SSE4-NEXT:    pxor %xmm1, %xmm1
; SSE4-NEXT:    pxor %xmm2, %xmm2
; SSE4-NEXT:    pblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2],xmm2[3,4,5,6,7]
; SSE4-NEXT:    movq {{.*#+}} xmm3 = [0,12827,45591,12375,0,0,0,0]
; SSE4-NEXT:    pmulhw %xmm0, %xmm3
; SSE4-NEXT:    paddw %xmm2, %xmm3
; SSE4-NEXT:    movdqa %xmm3, %xmm2
; SSE4-NEXT:    psrlw $15, %xmm2
; SSE4-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3],xmm1[4,5,6,7]
; SSE4-NEXT:    pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [u,512,4096,64,u,u,u,u]
; SSE4-NEXT:    pblendw {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3,4,5,6,7]
; SSE4-NEXT:    paddw %xmm2, %xmm3
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [1,654,23,5423,u,u,u,u]
; SSE4-NEXT:    psubw %xmm3, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: dont_fold_srem_one:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3 # [0,12827,45591,12375,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm2, %xmm3, %xmm2
; AVX1OR2-NEXT:    vpsrlw $15, %xmm2, %xmm3
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4,5,6,7]
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,512,4096,64,u,u,u,u]
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3,4,5,6,7]
; AVX1OR2-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_srem_one:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpxor %xmm1, %xmm1, %xmm1
; AVX512-NEXT:    vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
; AVX512-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3 # [0,12827,45591,12375,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm2, %xmm3, %xmm2
; AVX512-NEXT:    vpsrlw $15, %xmm2, %xmm3
; AVX512-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4,5,6,7]
; AVX512-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
; AVX512-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
  ret <4 x i16> %1
}

; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; SSE2-LABEL: dont_fold_urem_i16_smax:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movq {{.*#+}} xmm2 = [1,65535,1,0,0,0,0,0]
; SSE2-NEXT:    pmullw %xmm0, %xmm2
; SSE2-NEXT:    movq {{.*#+}} xmm1 = [0,32767,45591,12375,0,0,0,0]
; SSE2-NEXT:    pmulhw %xmm0, %xmm1
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,0,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm3
; SSE2-NEXT:    pand %xmm2, %xmm3
; SSE2-NEXT:    movdqa %xmm1, %xmm4
; SSE2-NEXT:    psraw $8, %xmm4
; SSE2-NEXT:    movdqa %xmm2, %xmm5
; SSE2-NEXT:    pandn %xmm4, %xmm5
; SSE2-NEXT:    por %xmm3, %xmm5
; SSE2-NEXT:    movdqa {{.*#+}} xmm3 = [65535,0,0,65535,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm5, %xmm4
; SSE2-NEXT:    pand %xmm3, %xmm4
; SSE2-NEXT:    psraw $4, %xmm5
; SSE2-NEXT:    pandn %xmm5, %xmm3
; SSE2-NEXT:    por %xmm4, %xmm3
; SSE2-NEXT:    movdqa %xmm3, %xmm4
; SSE2-NEXT:    pand %xmm2, %xmm4
; SSE2-NEXT:    psraw $2, %xmm3
; SSE2-NEXT:    pandn %xmm3, %xmm2
; SSE2-NEXT:    por %xmm4, %xmm2
; SSE2-NEXT:    psrlw $15, %xmm1
; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1,32768,23,5423,u,u,u,u]
; SSE2-NEXT:    psubw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_urem_i16_smax:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [1,65535,1,0,0,0,0,0]
; SSE4-NEXT:    pmullw %xmm0, %xmm1
; SSE4-NEXT:    movq {{.*#+}} xmm2 = [0,32767,45591,12375,0,0,0,0]
; SSE4-NEXT:    pmulhw %xmm0, %xmm2
; SSE4-NEXT:    paddw %xmm1, %xmm2
; SSE4-NEXT:    movdqa %xmm2, %xmm3
; SSE4-NEXT:    psrlw $15, %xmm3
; SSE4-NEXT:    pxor %xmm4, %xmm4
; SSE4-NEXT:    pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1,2,3],xmm4[4,5,6,7]
; SSE4-NEXT:    pmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,4,4096,64,u,u,u,u]
; SSE4-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; SSE4-NEXT:    paddw %xmm4, %xmm2
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [1,32768,23,5423,u,u,u,u]
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: dont_fold_urem_i16_smax:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,65535,1,0,u,u,u,u]
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [0,32767,45591,12375,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm1, %xmm2, %xmm2
; AVX1OR2-NEXT:    vpsrlw $15, %xmm2, %xmm3
; AVX1OR2-NEXT:    vpxor %xmm4, %xmm4, %xmm4
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1,2,3],xmm4[4,5,6,7]
; AVX1OR2-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,4,4096,64,u,u,u,u]
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
; AVX1OR2-NEXT:    vpaddw %xmm3, %xmm1, %xmm1
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_urem_i16_smax:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1,65535,1,0,u,u,u,u]
; AVX512-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [0,32767,45591,12375,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX512-NEXT:    vpsrlw $15, %xmm1, %xmm2
; AVX512-NEXT:    vpxor %xmm3, %xmm3, %xmm3
; AVX512-NEXT:    vpblendw {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3],xmm3[4,5,6,7]
; AVX512-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpaddw %xmm2, %xmm1, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,32768,23,5423,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
  ret <4 x i16> %1
}

; Don't fold i64 srem.
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
; SSE2-LABEL: dont_fold_srem_i64:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa %xmm1, %xmm2
; SSE2-NEXT:    movq %xmm1, %rcx
; SSE2-NEXT:    movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    imulq %rdx
; SSE2-NEXT:    addq %rcx, %rdx
; SSE2-NEXT:    movq %rdx, %rax
; SSE2-NEXT:    shrq $63, %rax
; SSE2-NEXT:    sarq $4, %rdx
; SSE2-NEXT:    addq %rax, %rdx
; SSE2-NEXT:    leaq (%rdx,%rdx,2), %rax
; SSE2-NEXT:    shlq $3, %rax
; SSE2-NEXT:    subq %rax, %rdx
; SSE2-NEXT:    addq %rcx, %rdx
; SSE2-NEXT:    movq %rdx, %xmm1
; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; SSE2-NEXT:    movq %xmm2, %rcx
; SSE2-NEXT:    movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    imulq %rdx
; SSE2-NEXT:    movq %rdx, %rax
; SSE2-NEXT:    shrq $63, %rax
; SSE2-NEXT:    sarq $11, %rdx
; SSE2-NEXT:    addq %rax, %rdx
; SSE2-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; SSE2-NEXT:    subq %rax, %rcx
; SSE2-NEXT:    movq %rcx, %xmm2
; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; SSE2-NEXT:    movq %xmm0, %rcx
; SSE2-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    imulq %rdx
; SSE2-NEXT:    movq %rdx, %rax
; SSE2-NEXT:    shrq $63, %rax
; SSE2-NEXT:    sarq $8, %rdx
; SSE2-NEXT:    addq %rax, %rdx
; SSE2-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; SSE2-NEXT:    subq %rax, %rcx
; SSE2-NEXT:    movq %rcx, %xmm0
; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_srem_i64:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movdqa %xmm1, %xmm2
; SSE4-NEXT:    movq %xmm1, %rcx
; SSE4-NEXT:    movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    imulq %rdx
; SSE4-NEXT:    addq %rcx, %rdx
; SSE4-NEXT:    movq %rdx, %rax
; SSE4-NEXT:    shrq $63, %rax
; SSE4-NEXT:    sarq $4, %rdx
; SSE4-NEXT:    addq %rax, %rdx
; SSE4-NEXT:    leaq (%rdx,%rdx,2), %rax
; SSE4-NEXT:    shlq $3, %rax
; SSE4-NEXT:    subq %rax, %rdx
; SSE4-NEXT:    addq %rcx, %rdx
; SSE4-NEXT:    movq %rdx, %xmm1
; SSE4-NEXT:    pextrq $1, %xmm2, %rcx
; SSE4-NEXT:    movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    imulq %rdx
; SSE4-NEXT:    movq %rdx, %rax
; SSE4-NEXT:    shrq $63, %rax
; SSE4-NEXT:    sarq $11, %rdx
; SSE4-NEXT:    addq %rax, %rdx
; SSE4-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; SSE4-NEXT:    subq %rax, %rcx
; SSE4-NEXT:    movq %rcx, %xmm2
; SSE4-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE4-NEXT:    pextrq $1, %xmm0, %rcx
; SSE4-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    imulq %rdx
; SSE4-NEXT:    movq %rdx, %rax
; SSE4-NEXT:    shrq $63, %rax
; SSE4-NEXT:    sarq $8, %rdx
; SSE4-NEXT:    addq %rax, %rdx
; SSE4-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; SSE4-NEXT:    subq %rax, %rcx
; SSE4-NEXT:    movq %rcx, %xmm0
; SSE4-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE4-NEXT:    retq
;
; AVX1-LABEL: dont_fold_srem_i64:
; AVX1:       # %bb.0:
; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT:    vmovq %xmm1, %rcx
; AVX1-NEXT:    movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    imulq %rdx
; AVX1-NEXT:    addq %rcx, %rdx
; AVX1-NEXT:    movq %rdx, %rax
; AVX1-NEXT:    shrq $63, %rax
; AVX1-NEXT:    sarq $4, %rdx
; AVX1-NEXT:    addq %rax, %rdx
; AVX1-NEXT:    leaq (%rdx,%rdx,2), %rax
; AVX1-NEXT:    shlq $3, %rax
; AVX1-NEXT:    subq %rax, %rdx
; AVX1-NEXT:    addq %rcx, %rdx
; AVX1-NEXT:    vmovq %rdx, %xmm2
; AVX1-NEXT:    vpextrq $1, %xmm1, %rcx
; AVX1-NEXT:    movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    imulq %rdx
; AVX1-NEXT:    movq %rdx, %rax
; AVX1-NEXT:    shrq $63, %rax
; AVX1-NEXT:    sarq $11, %rdx
; AVX1-NEXT:    addq %rax, %rdx
; AVX1-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; AVX1-NEXT:    subq %rax, %rcx
; AVX1-NEXT:    vmovq %rcx, %xmm1
; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX1-NEXT:    vpextrq $1, %xmm0, %rcx
; AVX1-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    imulq %rdx
; AVX1-NEXT:    movq %rdx, %rax
; AVX1-NEXT:    shrq $63, %rax
; AVX1-NEXT:    sarq $8, %rdx
; AVX1-NEXT:    addq %rax, %rdx
; AVX1-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; AVX1-NEXT:    subq %rax, %rcx
; AVX1-NEXT:    vmovq %rcx, %xmm0
; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT:    retq
;
; AVX2-LABEL: dont_fold_srem_i64:
; AVX2:       # %bb.0:
; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT:    vmovq %xmm1, %rcx
; AVX2-NEXT:    movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    imulq %rdx
; AVX2-NEXT:    addq %rcx, %rdx
; AVX2-NEXT:    movq %rdx, %rax
; AVX2-NEXT:    shrq $63, %rax
; AVX2-NEXT:    sarq $4, %rdx
; AVX2-NEXT:    addq %rax, %rdx
; AVX2-NEXT:    leaq (%rdx,%rdx,2), %rax
; AVX2-NEXT:    shlq $3, %rax
; AVX2-NEXT:    subq %rax, %rdx
; AVX2-NEXT:    addq %rcx, %rdx
; AVX2-NEXT:    vmovq %rdx, %xmm2
; AVX2-NEXT:    vpextrq $1, %xmm1, %rcx
; AVX2-NEXT:    movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    imulq %rdx
; AVX2-NEXT:    movq %rdx, %rax
; AVX2-NEXT:    shrq $63, %rax
; AVX2-NEXT:    sarq $11, %rdx
; AVX2-NEXT:    addq %rax, %rdx
; AVX2-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; AVX2-NEXT:    subq %rax, %rcx
; AVX2-NEXT:    vmovq %rcx, %xmm1
; AVX2-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT:    vpextrq $1, %xmm0, %rcx
; AVX2-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    imulq %rdx
; AVX2-NEXT:    movq %rdx, %rax
; AVX2-NEXT:    shrq $63, %rax
; AVX2-NEXT:    sarq $8, %rdx
; AVX2-NEXT:    addq %rax, %rdx
; AVX2-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; AVX2-NEXT:    subq %rax, %rcx
; AVX2-NEXT:    vmovq %rcx, %xmm0
; AVX2-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_srem_i64:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT:    vmovq %xmm1, %rcx
; AVX512-NEXT:    movabsq $-5614226457215950491, %rdx # imm = 0xB21642C8590B2165
; AVX512-NEXT:    movq %rcx, %rax
; AVX512-NEXT:    imulq %rdx
; AVX512-NEXT:    addq %rcx, %rdx
; AVX512-NEXT:    movq %rdx, %rax
; AVX512-NEXT:    shrq $63, %rax
; AVX512-NEXT:    sarq $4, %rdx
; AVX512-NEXT:    addq %rax, %rdx
; AVX512-NEXT:    leaq (%rdx,%rdx,2), %rax
; AVX512-NEXT:    shlq $3, %rax
; AVX512-NEXT:    subq %rax, %rdx
; AVX512-NEXT:    addq %rcx, %rdx
; AVX512-NEXT:    vpextrq $1, %xmm1, %rcx
; AVX512-NEXT:    vmovq %rdx, %xmm1
; AVX512-NEXT:    movabsq $6966426675817289639, %rdx # imm = 0x60ADB826E5E517A7
; AVX512-NEXT:    movq %rcx, %rax
; AVX512-NEXT:    imulq %rdx
; AVX512-NEXT:    movq %rdx, %rax
; AVX512-NEXT:    shrq $63, %rax
; AVX512-NEXT:    sarq $11, %rdx
; AVX512-NEXT:    addq %rax, %rdx
; AVX512-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; AVX512-NEXT:    subq %rax, %rcx
; AVX512-NEXT:    vmovq %rcx, %xmm2
; AVX512-NEXT:    vpextrq $1, %xmm0, %rcx
; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm2[0]
; AVX512-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX512-NEXT:    movq %rcx, %rax
; AVX512-NEXT:    imulq %rdx
; AVX512-NEXT:    movq %rdx, %rax
; AVX512-NEXT:    shrq $63, %rax
; AVX512-NEXT:    sarq $8, %rdx
; AVX512-NEXT:    addq %rax, %rdx
; AVX512-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; AVX512-NEXT:    subq %rax, %rcx
; AVX512-NEXT:    vmovq %rcx, %xmm1
; AVX512-NEXT:    vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; AVX512-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX512-NEXT:    retq
  %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
  ret <4 x i64> %1
}