llvm/test/CodeGen/X86/pr14161.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s

declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)

define <2 x i16> @good(ptr, ptr) {
; CHECK-LABEL: good:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movdqa (%rdi), %xmm0
; CHECK-NEXT:    pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT:    retq
entry:
  %2 = load <4 x i32>, ptr %0, align 16
  %3 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
  %4 = extractelement <4 x i32> %3, i32 0
  %5 = extractelement <4 x i32> %3, i32 1
  %6 = extractelement <4 x i32> %3, i32 2
  %7 = extractelement <4 x i32> %3, i32 3
  %8 = bitcast i32 %4 to <2 x i16>
  %9 = bitcast i32 %5 to <2 x i16>
  ret <2 x i16> %8
}

define <2 x i16> @bad(ptr, ptr) {
; CHECK-LABEL: bad:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = mem[1,1,1,1]
; CHECK-NEXT:    pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; CHECK-NEXT:    retq
entry:
  %2 = load <4 x i32>, ptr %0, align 16
  %3 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %2, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
  %4 = extractelement <4 x i32> %3, i32 0
  %5 = extractelement <4 x i32> %3, i32 1
  %6 = extractelement <4 x i32> %3, i32 2
  %7 = extractelement <4 x i32> %3, i32 3
  %8 = bitcast i32 %4 to <2 x i16>
  %9 = bitcast i32 %5 to <2 x i16>
  ret <2 x i16> %9
}