llvm/test/CodeGen/LoongArch/lsx/bitclr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define <16 x i8> @bitclri_v16i8(<16 x i8> %a) nounwind {
; CHECK-LABEL: bitclri_v16i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.b $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <16 x i8> %a, splat (i8 -5)
    ret <16 x i8> %0
}

define <8 x i16> @bitclri_v8i16(<8 x i16> %a) nounwind {
; CHECK-LABEL: bitclri_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.h $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <8 x i16> %a, splat (i16 -5)
    ret <8 x i16> %0
}

define <4 x i32> @bitclri_v4i32(<4 x i32> %a) nounwind {
; CHECK-LABEL: bitclri_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.w $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <4 x i32> %a, splat (i32 -5)
    ret <4 x i32> %0
}

define <2 x i64> @bitclri_v2i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: bitclri_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.d $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <2 x i64> %a, splat (i64 -5)
    ret <2 x i64> %0
}

define <4 x i32> @bitclri_v16i8_v4i32(<4 x i32> %a) nounwind {
; CHECK-LABEL: bitclri_v16i8_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vandi.b $vr0, $vr0, 251
; CHECK-NEXT:    ret
entry:
    %0 = and <4 x i32> %a, splat (i32 -67372037)
    ret <4 x i32> %0
}

define <4 x i32> @bitclri_v8i16_v4i32(<4 x i32> %a) nounwind {
; CHECK-LABEL: bitclri_v8i16_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.h $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <4 x i32> %a, splat (i32 -262149)
    ret <4 x i32> %0
}

define <2 x i64> @bitclri_v16i8_v2i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: bitclri_v16i8_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vandi.b $vr0, $vr0, 251
; CHECK-NEXT:    ret
entry:
    %0 = and <2 x i64> %a, splat (i64 -289360691352306693)
    ret <2 x i64> %0
}

define <2 x i64> @bitclri_v8i16_v2i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: bitclri_v8i16_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.h $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <2 x i64> %a, splat (i64 -1125917086973957)
    ret <2 x i64> %0
}

define <2 x i64> @bitclri_v4i32_v2i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: bitclri_v4i32_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vbitclri.w $vr0, $vr0, 2
; CHECK-NEXT:    ret
entry:
    %0 = and <2 x i64> %a, splat (i64 -17179869189)
    ret <2 x i64> %0
}