llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s

define amdgpu_kernel void @ds_swizzle(ptr addrspace(1) %out, i32 %src) nounwind {
; GFX7-LABEL: ds_swizzle:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_load_dword s2, s[4:5], 0xb
; GFX7-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-NEXT:    s_mov_b32 s3, 0xf000
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v0, s2
; GFX7-NEXT:    ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; GFX7-NEXT:    s_mov_b32 s2, -1
; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT:    s_endpgm
;
; GFX8-LABEL: ds_swizzle:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v0, s2
; GFX8-NEXT:    ds_swizzle_b32 v2, v0 offset:swizzle(BITMASK_PERM,"00p11")
; GFX8-NEXT:    v_mov_b32_e32 v0, s0
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
; GFX8-NEXT:    flat_store_dword v[0:1], v2
; GFX8-NEXT:    s_endpgm
  %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0
  store i32 %swizzle, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_ps i32 @ds_swizzle_s(i32 inreg %src) {
; CHECK-LABEL: ds_swizzle_s:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    v_mov_b32_e32 v0, s0
; CHECK-NEXT:    ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
; CHECK-NEXT:    ; return to shader part epilog
  %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
  ret i32 %swizzle
}

define amdgpu_ps i32 @ds_swizzle_v(i32 %src) {
; CHECK-LABEL: ds_swizzle_v:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_readfirstlane_b32 s0, v0
; CHECK-NEXT:    ; return to shader part epilog
  %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
  ret i32 %swizzle
}

declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0

attributes #0 = { nounwind readnone convergent }