llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-pre-emit-peephole -verify-machineinstrs  %s -o - | FileCheck %s
# Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0

---

name: skip_gws_init
body: |
  ; CHECK-LABEL: name: skip_gws_init
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec

  bb.2:
    S_ENDPGM 0
...

---

name: skip_gws_barrier
body: |
  ; CHECK-LABEL: name: skip_gws_barrier
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec

  bb.2:
    S_ENDPGM 0
...