llvm/test/CodeGen/RISCV/xqccmp_mvas_mvsa.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK32XQCCMP %s
# RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp -verify-machineinstrs -run-pass=riscv-move-merge -simplify-mir -o - %s | FileCheck -check-prefixes=CHECK64XQCCMP %s
---
name: mv
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x11, $x10
    ; CHECK32XQCCMP-LABEL: name: mv
    ; CHECK32XQCCMP: liveins: $x11, $x10
    ; CHECK32XQCCMP-NEXT: {{  $}}
    ; CHECK32XQCCMP-NEXT: $x9, $x8 = QC_CM_MVSA01 implicit $x10, implicit $x11
    ; CHECK32XQCCMP-NEXT: QC_CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11
    ; CHECK32XQCCMP-NEXT: PseudoRET
    ;
    ; CHECK64XQCCMP-LABEL: name: mv
    ; CHECK64XQCCMP: liveins: $x11, $x10
    ; CHECK64XQCCMP-NEXT: {{  $}}
    ; CHECK64XQCCMP-NEXT: $x9, $x8 = QC_CM_MVSA01 implicit $x10, implicit $x11
    ; CHECK64XQCCMP-NEXT: QC_CM_MVA01S killed $x9, $x8, implicit-def $x10, implicit-def $x11
    ; CHECK64XQCCMP-NEXT: PseudoRET
    $x8 = ADDI $x11, 0
    $x9 = ADDI $x10, 0
    $x10 = ADDI killed $x9, 0
    $x11 = ADDI $x8, 0
    PseudoRET
...