llvm/test/CodeGen/RISCV/pr145360.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s

define i32 @signed(i32 %0, ptr %1) {
; CHECK-LABEL: signed:
; CHECK:       # %bb.0:
; CHECK-NEXT:    sraiw a2, a0, 31
; CHECK-NEXT:    srliw a2, a2, 24
; CHECK-NEXT:    add a2, a0, a2
; CHECK-NEXT:    andi a2, a2, -256
; CHECK-NEXT:    subw a2, a0, a2
; CHECK-NEXT:    sraiw a0, a0, 8
; CHECK-NEXT:    sw a2, 0(a1)
; CHECK-NEXT:    ret
  %rem = srem i32 %0, 256
  store i32 %rem, ptr %1, align 4
  %div = sdiv exact i32 %0, 256
  ret i32 %div
}

define i32 @unsigned(i32 %0, ptr %1) {
; CHECK-LABEL: unsigned:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a2, a0, 32
; CHECK-NEXT:    lui a3, 699051
; CHECK-NEXT:    addi a3, a3, -1365
; CHECK-NEXT:    slli a4, a3, 32
; CHECK-NEXT:    mulhu a2, a2, a4
; CHECK-NEXT:    srli a2, a2, 36
; CHECK-NEXT:    slli a4, a2, 5
; CHECK-NEXT:    slli a2, a2, 3
; CHECK-NEXT:    subw a2, a2, a4
; CHECK-NEXT:    srliw a4, a0, 3
; CHECK-NEXT:    add a2, a0, a2
; CHECK-NEXT:    mulw a0, a4, a3
; CHECK-NEXT:    sw a2, 0(a1)
; CHECK-NEXT:    ret
  %rem = urem i32 %0, 24
  store i32 %rem, ptr %1, align 4
  %div = udiv exact i32 %0, 24
  ret i32 %div
}

define i32 @signed_div_first(i32 %0, ptr %1) {
; CHECK-LABEL: signed_div_first:
; CHECK:       # %bb.0:
; CHECK-NEXT:    sraiw a2, a0, 31
; CHECK-NEXT:    srliw a2, a2, 24
; CHECK-NEXT:    add a3, a0, a2
; CHECK-NEXT:    sraiw a2, a3, 8
; CHECK-NEXT:    andi a3, a3, -256
; CHECK-NEXT:    subw a0, a0, a3
; CHECK-NEXT:    sw a0, 0(a1)
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %div = sdiv exact i32 %0, 256
  %rem = srem i32 %0, 256
  store i32 %rem, ptr %1, align 4
  ret i32 %div
}

define i32 @unsigned_div_first(i32 %0, ptr %1) {
; CHECK-LABEL: unsigned_div_first:
; CHECK:       # %bb.0:
; CHECK-NEXT:    slli a2, a0, 32
; CHECK-NEXT:    lui a3, 699051
; CHECK-NEXT:    addi a3, a3, -1365
; CHECK-NEXT:    slli a3, a3, 32
; CHECK-NEXT:    mulhu a2, a2, a3
; CHECK-NEXT:    srli a2, a2, 36
; CHECK-NEXT:    slli a3, a2, 5
; CHECK-NEXT:    slli a4, a2, 3
; CHECK-NEXT:    subw a4, a4, a3
; CHECK-NEXT:    add a0, a0, a4
; CHECK-NEXT:    sw a0, 0(a1)
; CHECK-NEXT:    mv a0, a2
; CHECK-NEXT:    ret
  %div = udiv exact i32 %0, 24
  %rem = urem i32 %0, 24
  store i32 %rem, ptr %1, align 4
  ret i32 %div
}